[Mesa-dev] [PATCH 2/6] radeonsi: align shader binaries to CP DMA alignment for optimal prefetch

[Marek Olšák]

From: Marek Olšák <marek.olsak at amd.com>

---
 src/gallium/drivers/radeonsi/si_shader.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c
index f8eccdf..9ec6c06 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -5741,21 +5741,22 @@ int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
 			   (!epilog ? mainb->rodata_size : 0);
 	unsigned char *ptr;
 
 	assert(!prolog || !prolog->rodata_size);
 	assert((!prolog && !epilog) || !mainb->rodata_size);
 	assert(!epilog || !epilog->rodata_size);
 
 	r600_resource_reference(&shader->bo, NULL);
 	shader->bo = (struct r600_resource*)
 		     pipe_buffer_create(&sscreen->b.b, 0,
-					PIPE_USAGE_IMMUTABLE, bo_size);
+					PIPE_USAGE_IMMUTABLE,
+					align(bo_size, SI_CPDMA_ALIGNMENT));
 	if (!shader->bo)
 		return -ENOMEM;
 
 	/* Upload. */
 	ptr = sscreen->b.ws->buffer_map(shader->bo->buf, NULL,
 					PIPE_TRANSFER_READ_WRITE);
 
 	if (prolog) {
 		util_memcpy_cpu_to_le32(ptr, prolog->code, prolog->code_size);
 		ptr += prolog->code_size;
-- 
2.7.4