[Mesa-dev] [PATCH 3/3] radeonsi: remove SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER

[Nicolai Hähnle]

The series is

Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>

On 08.02.2017 20:06, Marek Olšák wrote:
> From: Marek Olšák <marek.olsak at amd.com>
>
> not necessary
> ---
>  src/gallium/drivers/radeonsi/si_pipe.h       | 3 ---
>  src/gallium/drivers/radeonsi/si_state.c      | 6 ++++--
>  src/gallium/drivers/radeonsi/si_state_draw.c | 3 ++-
>  3 files changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
> index 4075d2c..ffd1bce 100644
> --- a/src/gallium/drivers/radeonsi/si_pipe.h
> +++ b/src/gallium/drivers/radeonsi/si_pipe.h
> @@ -57,23 +57,20 @@
>  /* Framebuffer caches. */
>  #define SI_CONTEXT_FLUSH_AND_INV_DB	(R600_CONTEXT_PRIVATE_FLAG << 7)
>  #define SI_CONTEXT_FLUSH_AND_INV_CB	(R600_CONTEXT_PRIVATE_FLAG << 8)
>  /* Engine synchronization. */
>  #define SI_CONTEXT_VS_PARTIAL_FLUSH	(R600_CONTEXT_PRIVATE_FLAG << 9)
>  #define SI_CONTEXT_PS_PARTIAL_FLUSH	(R600_CONTEXT_PRIVATE_FLAG << 10)
>  #define SI_CONTEXT_CS_PARTIAL_FLUSH	(R600_CONTEXT_PRIVATE_FLAG << 11)
>  #define SI_CONTEXT_VGT_FLUSH		(R600_CONTEXT_PRIVATE_FLAG << 12)
>  #define SI_CONTEXT_VGT_STREAMOUT_SYNC	(R600_CONTEXT_PRIVATE_FLAG << 13)
>
> -#define SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER (SI_CONTEXT_FLUSH_AND_INV_CB | \
> -					      SI_CONTEXT_FLUSH_AND_INV_DB)
> -
>  #define SI_MAX_BORDER_COLORS	4096
>
>  struct si_compute;
>  struct hash_table;
>  struct u_suballocator;
>
>  struct si_screen {
>  	struct r600_common_screen	b;
>  	unsigned			gs_table_depth;
>  	unsigned			tess_offchip_block_dw_size;
> diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
> index de30076..5a163b1 100644
> --- a/src/gallium/drivers/radeonsi/si_state.c
> +++ b/src/gallium/drivers/radeonsi/si_state.c
> @@ -2364,21 +2364,22 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
>
>  	/* Only flush TC when changing the framebuffer state, because
>  	 * the only client not using TC that can change textures is
>  	 * the framebuffer.
>  	 *
>  	 * Flush all CB and DB caches here because all buffers can be used
>  	 * for write by both TC (with shader image stores) and CB/DB.
>  	 */
>  	sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
>  			 SI_CONTEXT_INV_GLOBAL_L2 |
> -			 SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER |
> +			 SI_CONTEXT_FLUSH_AND_INV_CB |
> +			 SI_CONTEXT_FLUSH_AND_INV_DB |
>  			 SI_CONTEXT_CS_PARTIAL_FLUSH;
>
>  	/* Take the maximum of the old and new count. If the new count is lower,
>  	 * dirtying is needed to disable the unbound colorbuffers.
>  	 */
>  	sctx->framebuffer.dirty_cbufs |=
>  		(1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
>  	sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
>
>  	si_dec_framebuffer_counters(&sctx->framebuffer.state);
> @@ -3567,21 +3568,22 @@ static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
>
>  	if (flags & PIPE_BARRIER_INDEX_BUFFER) {
>  		/* Indices are read through TC L2 since VI.
>  		 * L1 isn't used.
>  		 */
>  		if (sctx->screen->b.chip_class <= CIK)
>  			sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
>  	}
>
>  	if (flags & PIPE_BARRIER_FRAMEBUFFER)
> -		sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER;
> +		sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_CB |
> +				 SI_CONTEXT_FLUSH_AND_INV_DB;
>
>  	if (flags & (PIPE_BARRIER_FRAMEBUFFER |
>  		     PIPE_BARRIER_INDIRECT_BUFFER))
>  		sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
>  }
>
>  static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
>  {
>  	struct pipe_blend_state blend;
>
> diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
> index b6cf9a7..643ff74 100644
> --- a/src/gallium/drivers/radeonsi/si_state_draw.c
> +++ b/src/gallium/drivers/radeonsi/si_state_draw.c
> @@ -742,21 +742,22 @@ static void si_emit_surface_sync(struct r600_common_context *rctx,
>  	radeon_emit(cs, 0);               /* CP_COHER_BASE */
>  	radeon_emit(cs, 0x0000000A);      /* POLL_INTERVAL */
>  }
>
>  void si_emit_cache_flush(struct si_context *sctx)
>  {
>  	struct r600_common_context *rctx = &sctx->b;
>  	struct radeon_winsys_cs *cs = rctx->gfx.cs;
>  	uint32_t cp_coher_cntl = 0;
>
> -	if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER)
> +	if (rctx->flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
> +			   SI_CONTEXT_FLUSH_AND_INV_DB))
>  		sctx->b.num_fb_cache_flushes++;
>
>  	/* SI has a bug that it always flushes ICACHE and KCACHE if either
>  	 * bit is set. An alternative way is to write SQC_CACHES, but that
>  	 * doesn't seem to work reliably. Since the bug doesn't affect
>  	 * correctness (it only does more work than necessary) and
>  	 * the performance impact is likely negligible, there is no plan
>  	 * to add a workaround for it.
>  	 */
>
>