[Mesa-dev] [PATCH 4/4] radeonsi: allow unaligned vertex buffer offsets and strides on VI only

[Nicolai Hähnle]

On 11.02.2017 17:30, Marek Olšák wrote:
> From: Marek Olšák <marek.olsak at amd.com>
>
> so that we can disable u_vbuf for GL core profiles.
>
> SI-CIK fail piglit/draw-vertices, while VI doesn't.

Can you clarify, is this a regression?

If anything, I'd expect a potential regression on VI here, if you have a 
three-element GL_UNSIGNED_BYTE attribute whose last entry lines up 
precisely with the end of the buffer.

Nicolai

> ---
>  src/gallium/drivers/radeonsi/si_descriptors.c | 1 -
>  src/gallium/drivers/radeonsi/si_pipe.c        | 8 +++++---
>  2 files changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c
> index b0faf42..ace93ff 100644
> --- a/src/gallium/drivers/radeonsi/si_descriptors.c
> +++ b/src/gallium/drivers/radeonsi/si_descriptors.c
> @@ -1013,21 +1013,20 @@ bool si_upload_vertex_buffer_descriptors(struct si_context *sctx)
>  			 * up so that the hardware sees four components as
>  			 * being inside the buffer if and only if the first
>  			 * three components are in the buffer.
>  			 *
>  			 * Since the offset and stride are guaranteed to be
>  			 * 4-byte aligned, this alignment will never cross the
>  			 * winsys buffer boundary.
>  			 */
>  			size3 = (fix_size3 >> (2 * i)) & 3;
>  			if (vb->stride && size3) {
> -				assert(offset % 4 == 0 && vb->stride % 4 == 0);
>  				assert(size3 <= 2);
>  				desc[2] = align(desc[2], size3 * 2);
>  			}
>  		}
>
>  		desc[3] = velems->rsrc_word3[i];
>
>  		if (first_vb_use_mask & (1 << i)) {
>  			radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
>  					      (struct r600_resource*)vb->buffer,
> diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
> index 8806027..a3afab0 100644
> --- a/src/gallium/drivers/radeonsi/si_pipe.c
> +++ b/src/gallium/drivers/radeonsi/si_pipe.c
> @@ -353,23 +353,20 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
>  	case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
>  	case PIPE_CAP_SM3:
>  	case PIPE_CAP_SEAMLESS_CUBE_MAP:
>  	case PIPE_CAP_PRIMITIVE_RESTART:
>  	case PIPE_CAP_CONDITIONAL_RENDER:
>  	case PIPE_CAP_TEXTURE_BARRIER:
>  	case PIPE_CAP_INDEP_BLEND_ENABLE:
>  	case PIPE_CAP_INDEP_BLEND_FUNC:
>  	case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
>  	case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
> -	case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
> -	case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
> -	case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
>  	case PIPE_CAP_USER_INDEX_BUFFERS:
>  	case PIPE_CAP_USER_CONSTANT_BUFFERS:
>  	case PIPE_CAP_START_INSTANCE:
>  	case PIPE_CAP_NPOT_TEXTURES:
>  	case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
>  	case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
>  	case PIPE_CAP_VERTEX_COLOR_CLAMPED:
>  	case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
>          case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
>  	case PIPE_CAP_TGSI_INSTANCEID:
> @@ -455,20 +452,25 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
>
>  	case PIPE_CAP_GLSL_FEATURE_LEVEL:
>  		if (si_have_tgsi_compute(sscreen))
>  			return 450;
>  		return HAVE_LLVM >= 0x0309 ? 420 :
>  		       HAVE_LLVM >= 0x0307 ? 410 : 330;
>
>  	case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
>  		return MIN2(sscreen->b.info.max_alloc_size, INT_MAX);
>
> +	case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
> +	case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
> +	case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
> +		return sscreen->b.chip_class <= CIK;
> +
>  	/* Unsupported features. */
>  	case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
>  	case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
>  	case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
>  	case PIPE_CAP_USER_VERTEX_BUFFERS:
>  	case PIPE_CAP_FAKE_SW_MSAA:
>  	case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
>  	case PIPE_CAP_VERTEXID_NOBASE:
>  	case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
>  	case PIPE_CAP_TGSI_VOTE:
>