[Mesa-dev] [PATCH 2/3] Added support for disassembling SENDS and SENDSC.

Toni Lönnberg toni.lonnberg at intel.com
Mon Feb 13 16:44:31 UTC 2017


On 13.02.2017 16:02, Matt Turner wrote:
> There are a couple of fields in here that mirror the regular 1-2 src
> instructions. If adding them makes the code they're used in clearer,
> that's okay, but I'm finding them to make it difficult to see what's
> actually different.
>
>  From the docs, it looks like nearly all the changes are summarized by:
> new ExDesc field; new SelReg32Desc field; new SelReg32ExDesc field;
> and src1 fields are moved; something different about src0/dst AddrImm.
>
> The ones marked below are the same as in regular instructions. I don't
> know whether we should keep them. What are your thoughts?

They share some of the fields from the regular instructions, I only 
added the mirrored ones for readability. But if it pollutes the header 
file, they can be removed and I'll use the ones for the regular 
instructions.

> I don't see a function for SelReg32ExDesc. Don't we need that?
The documentation seems to have some ambiguity regarding this and as I 
didn't find a use case where the address registering was used, I don't 
know which way is correct.

One generic instruction format documentation lists both SelReg32Desc and 
SelReg32ExDesc. The general information about the instruction 
documentation only refers to SelReg32ExDesc as being used for selecting 
the scalar register for the descriptor. Then to make things even more 
complicated, the actual instruction format documentation doesn't list 
SelReg32ExDesc at all, just SelReg32Desc, and shows bit 61 as reserved.

So this would need more clarification from someone who actually knows 
what the hardware is expecting, I have no such contact information 
unfortunately.

-Toni
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