[Mesa-dev] [PATCH 4/4] radeonsi: allow unaligned vertex buffer offsets and strides on VI only
maraeo at gmail.com
Mon Feb 13 17:02:12 UTC 2017
On Mon, Feb 13, 2017 at 5:16 PM, Marek Olšák <maraeo at gmail.com> wrote:
> On Mon, Feb 13, 2017 at 4:42 PM, Nicolai Hähnle <nhaehnle at gmail.com> wrote:
>> On 11.02.2017 17:30, Marek Olšák wrote:
>>> From: Marek Olšák <marek.olsak at amd.com>
>>> so that we can disable u_vbuf for GL core profiles.
>>> SI-CIK fail piglit/draw-vertices, while VI doesn't.
>> Can you clarify, is this a regression?
>> If anything, I'd expect a potential regression on VI here, if you have a
>> three-element GL_UNSIGNED_BYTE attribute whose last entry lines up precisely
>> with the end of the buffer.
> I suspect that SI-CIK force dword formats (8_8_8_8 and 16_16) to be
> dword-aligned, while VI doesn't. This is configurable via
> SH_MEM_CONFIG on CIK-VI, and not configurable on SI.
> The amdgpu KMD sets SH_MEM_CONFIG.ALIGNMENT_MODE = UNALIGNED on CIK & VI.
> The radeon KMD sets SH_MEM_CONFIG.ALIGNMENT_MODE = DWORD on CIK.
> So I think we can at least enable unaligned loads on amdgpu+CIK now,
> and radeon+CIK only if we fix SH_MEM_CONFIG.
A new patch is coming.
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