[Mesa-dev] [PATCH] radv: adopt some init config workarounds from radeonsi.

[Edward O'Callaghan]

Reviewed-by: Edward O'Callaghan <funfunctor at folklore1984.net>

On 02/14/2017 05:25 PM, Dave Airlie wrote:
> From: Dave Airlie <airlied at redhat.com>
> 
> Just one bonaire fix.
> 
> Signed-off-by: Dave Airlie <airlied at redhat.com>
> ---
>  src/amd/vulkan/si_cmd_buffer.c | 11 +++++++++--
>  1 file changed, 9 insertions(+), 2 deletions(-)
> 
> diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
> index 881ff96..c6c5383 100644
> --- a/src/amd/vulkan/si_cmd_buffer.c
> +++ b/src/amd/vulkan/si_cmd_buffer.c
> @@ -378,6 +378,15 @@ si_emit_config(struct radv_physical_device *physical_device,
>  	radeon_set_context_reg(cs, R_028408_VGT_INDX_OFFSET, 0);
>  
>  	if (physical_device->rad_info.chip_class >= CIK) {
> +		/* If this is 0, Bonaire can hang even if GS isn't being used.
> +		 * Other chips are unaffected. These are suboptimal values,
> +		 * but we don't use on-chip GS.
> +		 */
> +		radeon_set_context_reg(cs, R_028A44_VGT_GS_ONCHIP_CNTL,
> +				       S_028A44_ES_VERTS_PER_SUBGRP(64) |
> +				       S_028A44_GS_PRIMS_PER_SUBGRP(4));
> +
> +		radeon_set_sh_reg(cs, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xffff));
>  		radeon_set_sh_reg(cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
>  		radeon_set_sh_reg(cs, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xffff));
>  		radeon_set_sh_reg(cs, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff));
> @@ -390,7 +399,6 @@ si_emit_config(struct radv_physical_device *physical_device,
>  			 *
>  			 * LATE_ALLOC_VS = 2 is the highest safe number.
>  			 */
> -			radeon_set_sh_reg(cs, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xffff));
>  			radeon_set_sh_reg(cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
>  			radeon_set_sh_reg(cs, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(2));
>  		} else {
> @@ -399,7 +407,6 @@ si_emit_config(struct radv_physical_device *physical_device,
>  			 * - VS can't execute on CU0.
>  			 * - If HS writes outputs to LDS, LS can't execute on CU0.
>  			 */
> -			radeon_set_sh_reg(cs, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xfffe));
>  			radeon_set_sh_reg(cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xfffe));
>  			radeon_set_sh_reg(cs, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(31));
>  		}
> 

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