[Mesa-dev] [PATCH v3 00/24] i965 Ivybridge ARB_gpu_shader_fp64 / OpenGL 4.0

[Samuel Iglesias Gonsálvez]

Hi,

This series implements initial support for Ivybridge FP64 for both
align16 and align1 backends, and with that we can enable FP64 and
OpenGL 4.0 in Ivybridge. 

These patches are available in our repository for testing. You can
clone it using the following command:

$ git clone -b i965-fp64-gen7-ivb-scalar-vec4-rc3 \
https://github.com/Igalia/mesa.git

This is the third version of the patch series that includes, among
other fixes, a working DF MOV INDIRECT support for IvyBridge,
improvements in the d2x legalization pass, improvements in the
regioning parameters handling for DF instructions on IVB, and validator
changes to detect misbehaviours in the generated code.

The only feature missing in this series would be register spilling of
64-bit data. With this series all existing FP64 tests in Piglit pass on
Ivybridge, except for ~36 tests that fail to spill registers (mostly
the same varying-packing tests that failed in the scalar backend
before Curro fixed the scalar spilling implementation for SIMD32).

Best regards,

Sam

Francisco Jerez (1):
  i965/fs: Get 64-bit indirect moves working on IVB.

Iago Toral Quiroga (1):
  i965/disasm: also print nibctrl in IVB for execsize=8

Juan A. Suarez Romero (9):
  i965/fs: add helper to retrieve instruction data size
  i965/fs: double regioning parameters and execsize for DF in IVB/BYT
  i965/fs: fix dst stride in IVB/BYT type conversions
  i965/fs: fix lower SIMD width for IVB/BYT's MOV_INDIRECT
  i965/vec4: keep original type when dealing with null registers
  i965/vec4: fix VEC4_OPCODE_FROM_DOUBLE for IVB/BYT
  i965/vec4: fix SIMD-width lowering for VEC4_OPCODE_FROM_DOUBLE in
    IVB/BYT
  i965/vec4: consider subregister offset in live variables
  i965/vec4: fix SIMD-with lowering for CMP/MOV instructions with
    conditional modifiers

Matt Turner (5):
  i965: Handle IVB DF differences in the validator.
  i965: Use <0,2,1> region for scalar DF sources on IVB/BYT.
  i965: Use source region <1,2,0> when converting to DF.
  i965/vec4: Fix exec size for MOVs SET_{HIGH,LOW}_32BIT.
  i965: Use correct VertStride on align16 instructions.

Samuel Iglesias Gonsálvez (8):
  i965/fs: clamp exec_size when an instruction has a scalar DF source
  i965/fs: generalize the legalization d2x pass
  i965/fs: lower all non-force_writemask_all DF instructions to SIMD4 on
    IVB/BYT
  i965/vec4: split DF instructions and later double its execsize in
    IVB/BYT
  i965/vec4: adapt setup_imm_df() to allow inserting instructions before
    another one
  i965: enable ARB_gpu_shader_fp64 for Ivybridge/Baytrail
  i965: enable OpenGL 4.0 to Ivybridge/Baytrail
  docs: mark GL_ARB_gpu_shader_fp64 and OpenGL 4.0 as supported by
    i965/gen7+

 docs/features.txt                                  |   4 +-
 src/mesa/drivers/dri/i965/brw_disasm.c             |   6 +-
 src/mesa/drivers/dri/i965/brw_eu_emit.c            |  72 ++++++++++++---
 src/mesa/drivers/dri/i965/brw_eu_validate.c        |  24 +++++
 src/mesa/drivers/dri/i965/brw_fs.cpp               |  43 ++++++---
 src/mesa/drivers/dri/i965/brw_fs.h                 |  14 +++
 src/mesa/drivers/dri/i965/brw_fs_generator.cpp     | 101 +++++++++++++++++++--
 src/mesa/drivers/dri/i965/brw_fs_lower_d2x.cpp     |  57 ++++++++----
 src/mesa/drivers/dri/i965/brw_ir_vec4.h            |  14 +++
 src/mesa/drivers/dri/i965/brw_vec4.cpp             | 100 ++++++++++++++++++--
 src/mesa/drivers/dri/i965/brw_vec4.h               |   2 +
 src/mesa/drivers/dri/i965/brw_vec4_generator.cpp   |  48 +++++++---
 .../drivers/dri/i965/brw_vec4_live_variables.cpp   |  12 ++-
 .../drivers/dri/i965/brw_vec4_live_variables.h     |   6 +-
 src/mesa/drivers/dri/i965/brw_vec4_nir.cpp         |  26 +++++-
 src/mesa/drivers/dri/i965/intel_extensions.c       |   4 +-
 src/mesa/drivers/dri/i965/intel_screen.c           |   6 +-
 17 files changed, 451 insertions(+), 88 deletions(-)

-- 
2.11.0