[Mesa-dev] [PATCH v3 06/24] i965: Use <0, 2, 1> region for scalar DF sources on IVB/BYT.

[Francisco Jerez]

Samuel Iglesias Gonsálvez <siglesias at igalia.com> writes:

> From: Matt Turner <mattst88 at gmail.com>
>
> On HSW+, scalar DF sources can be accessed using the normal <0,1,0>
> region, but on IVB and BYT DF regions must be programmed in terms of
> floats. A <0,2,1> region accomplishes this.
>
> v2:
> - Apply region <0,2,1> in brw_reg_from_fs_reg() (Curro).
>
> Signed-off-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
> ---
>  src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 9 +++++++++
>  1 file changed, 9 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> index b0d5732ac5c..2f60ddd8706 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> @@ -145,6 +145,15 @@ brw_reg_from_fs_reg(const struct gen_device_info *devinfo, fs_inst *inst,
>        unreachable("not reached");
>     }
>  

Maybe put a short comment here along the same lines as the commit
message so you don't need to run git-blame to figure out what this is
about?  Either way patch is:

Reviewed-by: Francisco Jerez <currojerez at riseup.net>

> +   if (devinfo->gen == 7 && !devinfo->is_haswell &&
> +       type_sz(reg->type) == 8 &&
> +       brw_reg.vstride == BRW_VERTICAL_STRIDE_0 &&
> +       brw_reg.width == BRW_WIDTH_1 &&
> +       brw_reg.hstride == BRW_HORIZONTAL_STRIDE_0) {
> +      brw_reg.width = BRW_WIDTH_2;
> +      brw_reg.hstride = BRW_HORIZONTAL_STRIDE_1;
> +   }
> +
>     return brw_reg;
>  }
>  
> -- 
> 2.11.0
>
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