[Mesa-dev] [PATCH 5/5] gallium: remove TGSI_OPCODE_CLAMP
Marek Olšák
maraeo at gmail.com
Thu Feb 16 22:00:44 UTC 2017
From: Marek Olšák <marek.olsak at amd.com>
Not used and not widely supported. Use MIN+MAX instead.
---
src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c | 16 ----------------
src/gallium/auxiliary/gallivm/lp_bld_tgsi_aos.c | 8 --------
src/gallium/auxiliary/nir/tgsi_to_nir.c | 11 -----------
src/gallium/auxiliary/tgsi/tgsi_exec.c | 16 ----------------
src/gallium/auxiliary/tgsi/tgsi_info.c | 2 +-
src/gallium/auxiliary/tgsi/tgsi_opcode_tmp.h | 1 -
src/gallium/auxiliary/tgsi/tgsi_util.c | 1 -
.../drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp | 10 ----------
src/gallium/drivers/r300/r300_tgsi_to_rc.c | 1 -
src/gallium/drivers/r600/r600_shader.c | 6 +++---
src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c | 3 ---
src/gallium/drivers/svga/svga_tgsi_insn.c | 1 -
src/gallium/include/pipe/p_shader_tokens.h | 2 +-
13 files changed, 5 insertions(+), 73 deletions(-)
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c
index e78cdb0..dc6568a 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c
@@ -103,35 +103,20 @@ static void
arr_emit(
const struct lp_build_tgsi_action * action,
struct lp_build_tgsi_context * bld_base,
struct lp_build_emit_data * emit_data)
{
LLVMValueRef tmp = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_ROUND, emit_data->args[0]);
emit_data->output[emit_data->chan] = LLVMBuildFPToSI(bld_base->base.gallivm->builder, tmp,
bld_base->uint_bld.vec_type, "");
}
-/* TGSI_OPCODE_CLAMP */
-static void
-clamp_emit(
- const struct lp_build_tgsi_action * action,
- struct lp_build_tgsi_context * bld_base,
- struct lp_build_emit_data * emit_data)
-{
- LLVMValueRef tmp;
- tmp = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MAX,
- emit_data->args[0],
- emit_data->args[1]);
- emit_data->output[emit_data->chan] = lp_build_emit_llvm_binary(bld_base,
- TGSI_OPCODE_MIN, tmp, emit_data->args[2]);
-}
-
/* DP* Helper */
static void
dp_fetch_args(
struct lp_build_tgsi_context * bld_base,
struct lp_build_emit_data * emit_data,
unsigned dp_components)
{
unsigned chan, src;
for (src = 0; src < 2; src++) {
@@ -1323,21 +1308,20 @@ lp_set_default_actions(struct lp_build_tgsi_context * bld_base)
bld_base->op_actions[TGSI_OPCODE_IF].fetch_args = scalar_unary_fetch_args;
bld_base->op_actions[TGSI_OPCODE_UIF].fetch_args = scalar_unary_fetch_args;
bld_base->op_actions[TGSI_OPCODE_KILL_IF].fetch_args = kil_fetch_args;
bld_base->op_actions[TGSI_OPCODE_KILL].fetch_args = kilp_fetch_args;
bld_base->op_actions[TGSI_OPCODE_RCP].fetch_args = scalar_unary_fetch_args;
bld_base->op_actions[TGSI_OPCODE_SIN].fetch_args = scalar_unary_fetch_args;
bld_base->op_actions[TGSI_OPCODE_LG2].fetch_args = scalar_unary_fetch_args;
bld_base->op_actions[TGSI_OPCODE_ADD].emit = add_emit;
bld_base->op_actions[TGSI_OPCODE_ARR].emit = arr_emit;
- bld_base->op_actions[TGSI_OPCODE_CLAMP].emit = clamp_emit;
bld_base->op_actions[TGSI_OPCODE_END].emit = end_emit;
bld_base->op_actions[TGSI_OPCODE_FRC].emit = frc_emit;
bld_base->op_actions[TGSI_OPCODE_LRP].emit = lrp_emit;
bld_base->op_actions[TGSI_OPCODE_MAD].emit = mad_emit;
bld_base->op_actions[TGSI_OPCODE_MOV].emit = mov_emit;
bld_base->op_actions[TGSI_OPCODE_MUL].emit = mul_emit;
bld_base->op_actions[TGSI_OPCODE_DIV].emit = fdiv_emit;
bld_base->op_actions[TGSI_OPCODE_RCP].emit = rcp_emit;
bld_base->op_actions[TGSI_OPCODE_UARL].emit = mov_emit;
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_aos.c b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_aos.c
index 6c177b0..2bd4291 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_aos.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_aos.c
@@ -602,28 +602,20 @@ lp_emit_instruction_aos(
case TGSI_OPCODE_DP2A:
return FALSE;
case TGSI_OPCODE_FRC:
src0 = lp_build_emit_fetch(&bld->bld_base, inst, 0, LP_CHAN_ALL);
tmp0 = lp_build_floor(&bld->bld_base.base, src0);
dst0 = lp_build_sub(&bld->bld_base.base, src0, tmp0);
break;
- case TGSI_OPCODE_CLAMP:
- src0 = lp_build_emit_fetch(&bld->bld_base, inst, 0, LP_CHAN_ALL);
- src1 = lp_build_emit_fetch(&bld->bld_base, inst, 1, LP_CHAN_ALL);
- src2 = lp_build_emit_fetch(&bld->bld_base, inst, 2, LP_CHAN_ALL);
- tmp0 = lp_build_max(&bld->bld_base.base, src0, src1);
- dst0 = lp_build_min(&bld->bld_base.base, tmp0, src2);
- break;
-
case TGSI_OPCODE_FLR:
src0 = lp_build_emit_fetch(&bld->bld_base, inst, 0, LP_CHAN_ALL);
dst0 = lp_build_floor(&bld->bld_base.base, src0);
break;
case TGSI_OPCODE_ROUND:
src0 = lp_build_emit_fetch(&bld->bld_base, inst, 0, LP_CHAN_ALL);
dst0 = lp_build_round(&bld->bld_base.base, src0);
break;
diff --git a/src/gallium/auxiliary/nir/tgsi_to_nir.c b/src/gallium/auxiliary/nir/tgsi_to_nir.c
index f3e8700..5de74e0 100644
--- a/src/gallium/auxiliary/nir/tgsi_to_nir.c
+++ b/src/gallium/auxiliary/nir/tgsi_to_nir.c
@@ -979,26 +979,20 @@ ttn_sle(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
ttn_move_dest(b, dest, nir_sge(b, src[1], src[0]));
}
static void
ttn_sgt(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
{
ttn_move_dest(b, dest, nir_slt(b, src[1], src[0]));
}
static void
-ttn_clamp(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
-{
- ttn_move_dest(b, dest, nir_fmin(b, nir_fmax(b, src[0], src[1]), src[2]));
-}
-
-static void
ttn_xpd(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
{
ttn_move_dest_masked(b, dest,
nir_fsub(b,
nir_fmul(b,
ttn_swizzle(b, src[0], Y, Z, X, X),
ttn_swizzle(b, src[1], Z, X, Y, X)),
nir_fmul(b,
ttn_swizzle(b, src[1], Y, Z, X, X),
ttn_swizzle(b, src[0], Z, X, Y, X))),
@@ -1532,21 +1526,20 @@ static const nir_op op_trans[TGSI_OPCODE_LAST] = {
[TGSI_OPCODE_DST] = 0,
[TGSI_OPCODE_MIN] = nir_op_fmin,
[TGSI_OPCODE_MAX] = nir_op_fmax,
[TGSI_OPCODE_SLT] = nir_op_slt,
[TGSI_OPCODE_SGE] = nir_op_sge,
[TGSI_OPCODE_MAD] = nir_op_ffma,
[TGSI_OPCODE_LRP] = 0,
[TGSI_OPCODE_SQRT] = nir_op_fsqrt,
[TGSI_OPCODE_DP2A] = 0,
[TGSI_OPCODE_FRC] = nir_op_ffract,
- [TGSI_OPCODE_CLAMP] = 0,
[TGSI_OPCODE_FLR] = nir_op_ffloor,
[TGSI_OPCODE_ROUND] = nir_op_fround_even,
[TGSI_OPCODE_EX2] = nir_op_fexp2,
[TGSI_OPCODE_LG2] = nir_op_flog2,
[TGSI_OPCODE_POW] = nir_op_fpow,
[TGSI_OPCODE_XPD] = 0,
[TGSI_OPCODE_DPH] = 0,
[TGSI_OPCODE_COS] = nir_op_fcos,
[TGSI_OPCODE_DDX] = nir_op_fddx,
[TGSI_OPCODE_DDY] = nir_op_fddy,
@@ -1758,24 +1751,20 @@ ttn_emit_instruction(struct ttn_compile *c)
break;
case TGSI_OPCODE_DST:
ttn_dst(b, op_trans[tgsi_op], dest, src);
break;
case TGSI_OPCODE_LIT:
ttn_lit(b, op_trans[tgsi_op], dest, src);
break;
- case TGSI_OPCODE_CLAMP:
- ttn_clamp(b, op_trans[tgsi_op], dest, src);
- break;
-
case TGSI_OPCODE_XPD:
ttn_xpd(b, op_trans[tgsi_op], dest, src);
break;
case TGSI_OPCODE_DP2:
ttn_dp2(b, op_trans[tgsi_op], dest, src);
break;
case TGSI_OPCODE_DP3:
ttn_dp3(b, op_trans[tgsi_op], dest, src);
diff --git a/src/gallium/auxiliary/tgsi/tgsi_exec.c b/src/gallium/auxiliary/tgsi/tgsi_exec.c
index 2135ad1..3c15306 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_exec.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_exec.c
@@ -120,32 +120,20 @@ static void
micro_ceil(union tgsi_exec_channel *dst,
const union tgsi_exec_channel *src)
{
dst->f[0] = ceilf(src->f[0]);
dst->f[1] = ceilf(src->f[1]);
dst->f[2] = ceilf(src->f[2]);
dst->f[3] = ceilf(src->f[3]);
}
static void
-micro_clamp(union tgsi_exec_channel *dst,
- const union tgsi_exec_channel *src0,
- const union tgsi_exec_channel *src1,
- const union tgsi_exec_channel *src2)
-{
- dst->f[0] = src0->f[0] < src1->f[0] ? src1->f[0] : src0->f[0] > src2->f[0] ? src2->f[0] : src0->f[0];
- dst->f[1] = src0->f[1] < src1->f[1] ? src1->f[1] : src0->f[1] > src2->f[1] ? src2->f[1] : src0->f[1];
- dst->f[2] = src0->f[2] < src1->f[2] ? src1->f[2] : src0->f[2] > src2->f[2] ? src2->f[2] : src0->f[2];
- dst->f[3] = src0->f[3] < src1->f[3] ? src1->f[3] : src0->f[3] > src2->f[3] ? src2->f[3] : src0->f[3];
-}
-
-static void
micro_cmp(union tgsi_exec_channel *dst,
const union tgsi_exec_channel *src0,
const union tgsi_exec_channel *src1,
const union tgsi_exec_channel *src2)
{
dst->f[0] = src0->f[0] < 0.0f ? src1->f[0] : src2->f[0];
dst->f[1] = src0->f[1] < 0.0f ? src1->f[1] : src2->f[1];
dst->f[2] = src0->f[2] < 0.0f ? src1->f[2] : src2->f[2];
dst->f[3] = src0->f[3] < 0.0f ? src1->f[3] : src2->f[3];
}
@@ -5227,24 +5215,20 @@ exec_instruction(
break;
case TGSI_OPCODE_DP2A:
exec_dp2a(mach, inst);
break;
case TGSI_OPCODE_FRC:
exec_vector_unary(mach, inst, micro_frc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
break;
- case TGSI_OPCODE_CLAMP:
- exec_vector_trinary(mach, inst, micro_clamp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
- break;
-
case TGSI_OPCODE_FLR:
exec_vector_unary(mach, inst, micro_flr, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
break;
case TGSI_OPCODE_ROUND:
exec_vector_unary(mach, inst, micro_rnd, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
break;
case TGSI_OPCODE_EX2:
exec_scalar_unary(mach, inst, micro_exp2, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
diff --git a/src/gallium/auxiliary/tgsi/tgsi_info.c b/src/gallium/auxiliary/tgsi/tgsi_info.c
index 4509b95..f8bedee 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_info.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_info.c
@@ -55,21 +55,21 @@ static const struct tgsi_opcode_info opcode_info[TGSI_OPCODE_LAST] =
{ 1, 2, 0, 0, 0, 0, 0, COMP, "SGE", TGSI_OPCODE_SGE },
{ 1, 3, 0, 0, 0, 0, 0, COMP, "MAD", TGSI_OPCODE_MAD },
{ 1, 2, 0, 0, 0, 0, 0, COMP, "", 17 }, /* removed */
{ 1, 3, 0, 0, 0, 0, 0, COMP, "LRP", TGSI_OPCODE_LRP },
{ 1, 3, 0, 0, 0, 0, 0, COMP, "FMA", TGSI_OPCODE_FMA },
{ 1, 1, 0, 0, 0, 0, 0, REPL, "SQRT", TGSI_OPCODE_SQRT },
{ 1, 3, 0, 0, 0, 0, 0, REPL, "DP2A", TGSI_OPCODE_DP2A },
{ 1, 1, 0, 0, 0, 0, 0, COMP, "F2U64", TGSI_OPCODE_F2U64 },
{ 1, 1, 0, 0, 0, 0, 0, COMP, "F2I64", TGSI_OPCODE_F2I64 },
{ 1, 1, 0, 0, 0, 0, 0, COMP, "FRC", TGSI_OPCODE_FRC },
- { 1, 3, 0, 0, 0, 0, 0, COMP, "CLAMP", TGSI_OPCODE_CLAMP },
+ { 1, 3, 0, 0, 0, 0, 0, COMP, "", 25 }, /* removed */
{ 1, 1, 0, 0, 0, 0, 0, COMP, "FLR", TGSI_OPCODE_FLR },
{ 1, 1, 0, 0, 0, 0, 0, COMP, "ROUND", TGSI_OPCODE_ROUND },
{ 1, 1, 0, 0, 0, 0, 0, REPL, "EX2", TGSI_OPCODE_EX2 },
{ 1, 1, 0, 0, 0, 0, 0, REPL, "LG2", TGSI_OPCODE_LG2 },
{ 1, 2, 0, 0, 0, 0, 0, REPL, "POW", TGSI_OPCODE_POW },
{ 1, 2, 0, 0, 0, 0, 0, COMP, "XPD", TGSI_OPCODE_XPD },
{ 1, 1, 0, 0, 0, 0, 0, COMP, "U2I64", TGSI_OPCODE_U2I64 },
{ 1, 1, 0, 0, 0, 0, 0, COMP, "", 33 }, /* removed */
{ 1, 1, 0, 0, 0, 0, 0, COMP, "I2I64", TGSI_OPCODE_I2I64 },
{ 1, 2, 0, 0, 0, 0, 0, REPL, "DPH", TGSI_OPCODE_DPH },
diff --git a/src/gallium/auxiliary/tgsi/tgsi_opcode_tmp.h b/src/gallium/auxiliary/tgsi/tgsi_opcode_tmp.h
index 13c443f..ab73fab 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_opcode_tmp.h
+++ b/src/gallium/auxiliary/tgsi/tgsi_opcode_tmp.h
@@ -70,21 +70,20 @@ OP12(DP4)
OP12(DST)
OP12(MIN)
OP12(MAX)
OP12(SLT)
OP12(SGE)
OP13(MAD)
OP13(LRP)
OP11(SQRT)
OP13(DP2A)
OP11(FRC)
-OP13(CLAMP)
OP11(FLR)
OP11(ROUND)
OP11(EX2)
OP11(LG2)
OP12(POW)
OP12(XPD)
OP12(DPH)
OP11(COS)
OP11(DDX)
OP11(DDY)
diff --git a/src/gallium/auxiliary/tgsi/tgsi_util.c b/src/gallium/auxiliary/tgsi/tgsi_util.c
index 4a6a2ae..f6d2d3f 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_util.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_util.c
@@ -189,21 +189,20 @@ tgsi_util_get_inst_usage_mask(const struct tgsi_full_instruction *inst,
case TGSI_OPCODE_ADD:
case TGSI_OPCODE_MIN:
case TGSI_OPCODE_MAX:
case TGSI_OPCODE_SLT:
case TGSI_OPCODE_SGE:
case TGSI_OPCODE_MAD:
case TGSI_OPCODE_LRP:
case TGSI_OPCODE_FMA:
case TGSI_OPCODE_FRC:
case TGSI_OPCODE_CEIL:
- case TGSI_OPCODE_CLAMP:
case TGSI_OPCODE_FLR:
case TGSI_OPCODE_ROUND:
case TGSI_OPCODE_POW:
case TGSI_OPCODE_COS:
case TGSI_OPCODE_SIN:
case TGSI_OPCODE_DDX:
case TGSI_OPCODE_DDY:
case TGSI_OPCODE_SEQ:
case TGSI_OPCODE_SGT:
case TGSI_OPCODE_SLE:
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
index d634d2d..fdaa628 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
@@ -3359,30 +3359,20 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn)
val0 = getScratch();
mkOp1(OP_FLOOR, TYPE_F32, val0, src0);
mkOp2(OP_SUB, TYPE_F32, dst0[c], src0, val0);
}
break;
case TGSI_OPCODE_ROUND:
FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
mkCvt(OP_CVT, TYPE_F32, dst0[c], TYPE_F32, fetchSrc(0, c))
->rnd = ROUND_NI;
break;
- case TGSI_OPCODE_CLAMP:
- FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
- src0 = fetchSrc(0, c);
- src1 = fetchSrc(1, c);
- src2 = fetchSrc(2, c);
- val0 = getScratch();
- mkOp2(OP_MIN, TYPE_F32, val0, src0, src1);
- mkOp2(OP_MAX, TYPE_F32, dst0[c], val0, src2);
- }
- break;
case TGSI_OPCODE_SLT:
case TGSI_OPCODE_SGE:
case TGSI_OPCODE_SEQ:
case TGSI_OPCODE_SGT:
case TGSI_OPCODE_SLE:
case TGSI_OPCODE_SNE:
case TGSI_OPCODE_FSEQ:
case TGSI_OPCODE_FSGE:
case TGSI_OPCODE_FSLT:
case TGSI_OPCODE_FSNE:
diff --git a/src/gallium/drivers/r300/r300_tgsi_to_rc.c b/src/gallium/drivers/r300/r300_tgsi_to_rc.c
index 59dfa05..a9e3d6d 100644
--- a/src/gallium/drivers/r300/r300_tgsi_to_rc.c
+++ b/src/gallium/drivers/r300/r300_tgsi_to_rc.c
@@ -46,21 +46,20 @@ static unsigned translate_opcode(unsigned opcode)
case TGSI_OPCODE_DP4: return RC_OPCODE_DP4;
case TGSI_OPCODE_DST: return RC_OPCODE_DST;
case TGSI_OPCODE_MIN: return RC_OPCODE_MIN;
case TGSI_OPCODE_MAX: return RC_OPCODE_MAX;
case TGSI_OPCODE_SLT: return RC_OPCODE_SLT;
case TGSI_OPCODE_SGE: return RC_OPCODE_SGE;
case TGSI_OPCODE_MAD: return RC_OPCODE_MAD;
case TGSI_OPCODE_LRP: return RC_OPCODE_LRP;
/* case TGSI_OPCODE_DP2A: return RC_OPCODE_DP2A; */
case TGSI_OPCODE_FRC: return RC_OPCODE_FRC;
- case TGSI_OPCODE_CLAMP: return RC_OPCODE_CLAMP;
case TGSI_OPCODE_FLR: return RC_OPCODE_FLR;
case TGSI_OPCODE_ROUND: return RC_OPCODE_ROUND;
case TGSI_OPCODE_EX2: return RC_OPCODE_EX2;
case TGSI_OPCODE_LG2: return RC_OPCODE_LG2;
case TGSI_OPCODE_POW: return RC_OPCODE_POW;
case TGSI_OPCODE_XPD: return RC_OPCODE_XPD;
case TGSI_OPCODE_DPH: return RC_OPCODE_DPH;
case TGSI_OPCODE_COS: return RC_OPCODE_COS;
case TGSI_OPCODE_DDX: return RC_OPCODE_DDX;
case TGSI_OPCODE_DDY: return RC_OPCODE_DDY;
diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index b80a3f8..8cb3f8b 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -9090,21 +9090,21 @@ static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[]
[TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
[TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
[TGSI_OPCODE_MAD] = { ALU_OP3_MULADD_IEEE, tgsi_op3},
[TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
[TGSI_OPCODE_FMA] = { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, tgsi_trans_srcx_replicate},
[TGSI_OPCODE_DP2A] = { ALU_OP0_NOP, tgsi_unsupported},
[22] = { ALU_OP0_NOP, tgsi_unsupported},
[23] = { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
- [TGSI_OPCODE_CLAMP] = { ALU_OP0_NOP, tgsi_unsupported},
+ [25] = { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
[TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
[TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
[TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
[TGSI_OPCODE_POW] = { ALU_OP0_NOP, tgsi_pow},
[TGSI_OPCODE_XPD] = { ALU_OP0_NOP, tgsi_xpd},
[32] = { ALU_OP0_NOP, tgsi_unsupported},
[33] = { ALU_OP0_NOP, tgsi_unsupported},
[34] = { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_DPH] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
@@ -9288,21 +9288,21 @@ static const struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] =
[TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
[TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
[TGSI_OPCODE_MAD] = { ALU_OP3_MULADD_IEEE, tgsi_op3},
[TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
[TGSI_OPCODE_FMA] = { ALU_OP3_FMA, tgsi_op3},
[TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, tgsi_trans_srcx_replicate},
[TGSI_OPCODE_DP2A] = { ALU_OP0_NOP, tgsi_unsupported},
[22] = { ALU_OP0_NOP, tgsi_unsupported},
[23] = { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
- [TGSI_OPCODE_CLAMP] = { ALU_OP0_NOP, tgsi_unsupported},
+ [25] = { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
[TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
[TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
[TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
[TGSI_OPCODE_POW] = { ALU_OP0_NOP, tgsi_pow},
[TGSI_OPCODE_XPD] = { ALU_OP0_NOP, tgsi_xpd},
[32] = { ALU_OP0_NOP, tgsi_unsupported},
[33] = { ALU_OP0_NOP, tgsi_unsupported},
[34] = { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_DPH] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
@@ -9511,21 +9511,21 @@ static const struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] =
[TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
[TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
[TGSI_OPCODE_MAD] = { ALU_OP3_MULADD_IEEE, tgsi_op3},
[TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
[TGSI_OPCODE_FMA] = { ALU_OP3_FMA, tgsi_op3},
[TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, cayman_emit_float_instr},
[TGSI_OPCODE_DP2A] = { ALU_OP0_NOP, tgsi_unsupported},
[22] = { ALU_OP0_NOP, tgsi_unsupported},
[23] = { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
- [TGSI_OPCODE_CLAMP] = { ALU_OP0_NOP, tgsi_unsupported},
+ [25] = { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
[TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
[TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, cayman_emit_float_instr},
[TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, cayman_emit_float_instr},
[TGSI_OPCODE_POW] = { ALU_OP0_NOP, cayman_pow},
[TGSI_OPCODE_XPD] = { ALU_OP0_NOP, tgsi_xpd},
[32] = { ALU_OP0_NOP, tgsi_unsupported},
[33] = { ALU_OP0_NOP, tgsi_unsupported},
[34] = { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_DPH] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
diff --git a/src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c b/src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c
index 085fd5b..f0199c72 100644
--- a/src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c
+++ b/src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c
@@ -768,23 +768,20 @@ void si_shader_context_init_alu(struct lp_build_tgsi_context *bld_base)
lp_set_default_actions(bld_base);
bld_base->op_actions[TGSI_OPCODE_AND].emit = emit_and;
bld_base->op_actions[TGSI_OPCODE_ARL].emit = emit_arl;
bld_base->op_actions[TGSI_OPCODE_BFI].emit = emit_bfi;
bld_base->op_actions[TGSI_OPCODE_BREV].emit = build_tgsi_intrinsic_nomem;
bld_base->op_actions[TGSI_OPCODE_BREV].intr_name =
HAVE_LLVM >= 0x0308 ? "llvm.bitreverse.i32" : "llvm.AMDGPU.brev";
bld_base->op_actions[TGSI_OPCODE_CEIL].emit = build_tgsi_intrinsic_nomem;
bld_base->op_actions[TGSI_OPCODE_CEIL].intr_name = "llvm.ceil.f32";
- bld_base->op_actions[TGSI_OPCODE_CLAMP].emit = build_tgsi_intrinsic_nomem;
- bld_base->op_actions[TGSI_OPCODE_CLAMP].intr_name =
- HAVE_LLVM >= 0x0308 ? "llvm.AMDGPU.clamp." : "llvm.AMDIL.clamp.";
bld_base->op_actions[TGSI_OPCODE_CMP].emit = emit_cmp;
bld_base->op_actions[TGSI_OPCODE_COS].emit = build_tgsi_intrinsic_nomem;
bld_base->op_actions[TGSI_OPCODE_COS].intr_name = "llvm.cos.f32";
bld_base->op_actions[TGSI_OPCODE_DABS].emit = build_tgsi_intrinsic_nomem;
bld_base->op_actions[TGSI_OPCODE_DABS].intr_name = "llvm.fabs.f64";
bld_base->op_actions[TGSI_OPCODE_DFMA].emit = build_tgsi_intrinsic_nomem;
bld_base->op_actions[TGSI_OPCODE_DFMA].intr_name = "llvm.fma.f64";
bld_base->op_actions[TGSI_OPCODE_DFRAC].emit = emit_frac;
bld_base->op_actions[TGSI_OPCODE_DIV].emit = emit_fdiv;
bld_base->op_actions[TGSI_OPCODE_DNEG].emit = emit_dneg;
diff --git a/src/gallium/drivers/svga/svga_tgsi_insn.c b/src/gallium/drivers/svga/svga_tgsi_insn.c
index 0efd72d..fc3ec5e 100644
--- a/src/gallium/drivers/svga/svga_tgsi_insn.c
+++ b/src/gallium/drivers/svga/svga_tgsi_insn.c
@@ -2993,21 +2993,20 @@ svga_emit_instruction(struct svga_shader_emitter *emit,
case TGSI_OPCODE_RET:
/* This is a noop -- we tell mesa that we can't support RET
* within a function (early return), so this will always be
* followed by an ENDSUB.
*/
return TRUE;
/* These aren't actually used by any of the frontends we care
* about:
*/
- case TGSI_OPCODE_CLAMP:
case TGSI_OPCODE_AND:
case TGSI_OPCODE_OR:
case TGSI_OPCODE_I2F:
case TGSI_OPCODE_NOT:
case TGSI_OPCODE_SHL:
case TGSI_OPCODE_ISHR:
case TGSI_OPCODE_XOR:
return FALSE;
case TGSI_OPCODE_IF:
diff --git a/src/gallium/include/pipe/p_shader_tokens.h b/src/gallium/include/pipe/p_shader_tokens.h
index 1c8d87c..1118604 100644
--- a/src/gallium/include/pipe/p_shader_tokens.h
+++ b/src/gallium/include/pipe/p_shader_tokens.h
@@ -347,21 +347,21 @@ struct tgsi_property_data {
#define TGSI_OPCODE_SGE 15
#define TGSI_OPCODE_MAD 16
/* gap */
#define TGSI_OPCODE_LRP 18
#define TGSI_OPCODE_FMA 19
#define TGSI_OPCODE_SQRT 20
#define TGSI_OPCODE_DP2A 21
#define TGSI_OPCODE_F2U64 22
#define TGSI_OPCODE_F2I64 23
#define TGSI_OPCODE_FRC 24
-#define TGSI_OPCODE_CLAMP 25
+/* gap */
#define TGSI_OPCODE_FLR 26
#define TGSI_OPCODE_ROUND 27
#define TGSI_OPCODE_EX2 28
#define TGSI_OPCODE_LG2 29
#define TGSI_OPCODE_POW 30
#define TGSI_OPCODE_XPD 31
#define TGSI_OPCODE_U2I64 32
/* gap */
#define TGSI_OPCODE_I2I64 34
#define TGSI_OPCODE_DPH 35
--
2.7.4
More information about the mesa-dev
mailing list