[Mesa-dev] [PATCH 1/2] i965: Add an OUT_BATCH64() macro.

[Ben Widawsky]

On 17-02-14 13:45:48, Kenneth Graunke wrote:
>This is more convenient than OUT_BATCH'ing both halves.
>

It also is potentially more efficient (probably immeasurable).

Reviewed-by: Ben Widawsky <ben at bwidawsk.net>

>Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
>Cc: Ben Widawsky <ben at bwidawsk.net>
>---
> src/mesa/drivers/dri/i965/gen8_depth_state.c  | 3 +--
> src/mesa/drivers/dri/i965/gen8_ds_state.c     | 3 +--
> src/mesa/drivers/dri/i965/gen8_gs_state.c     | 3 +--
> src/mesa/drivers/dri/i965/gen8_hs_state.c     | 3 +--
> src/mesa/drivers/dri/i965/gen8_ps_state.c     | 3 +--
> src/mesa/drivers/dri/i965/gen8_vs_state.c     | 3 +--
> src/mesa/drivers/dri/i965/intel_batchbuffer.h | 1 +
> 7 files changed, 7 insertions(+), 12 deletions(-)
>
>diff --git a/src/mesa/drivers/dri/i965/gen8_depth_state.c b/src/mesa/drivers/dri/i965/gen8_depth_state.c
>index a7e61354fd5..c085246bc92 100644
>--- a/src/mesa/drivers/dri/i965/gen8_depth_state.c
>+++ b/src/mesa/drivers/dri/i965/gen8_depth_state.c
>@@ -72,8 +72,7 @@ emit_depth_packets(struct brw_context *brw,
>       OUT_RELOC64(depth_mt->bo,
>                   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
>    } else {
>-      OUT_BATCH(0);
>-      OUT_BATCH(0);
>+      OUT_BATCH64(0);
>    }
>    OUT_BATCH(((width - 1) << 4) | ((height - 1) << 18) | lod);
>    OUT_BATCH(((depth - 1) << 21) | (min_array_element << 10) | mocs_wb);
>diff --git a/src/mesa/drivers/dri/i965/gen8_ds_state.c b/src/mesa/drivers/dri/i965/gen8_ds_state.c
>index ee2f82e1098..55738fd1ffc 100644
>--- a/src/mesa/drivers/dri/i965/gen8_ds_state.c
>+++ b/src/mesa/drivers/dri/i965/gen8_ds_state.c
>@@ -56,8 +56,7 @@ gen8_upload_ds_state(struct brw_context *brw)
>                      I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
>                      ffs(stage_state->per_thread_scratch) - 11);
>       } else {
>-         OUT_BATCH(0);
>-         OUT_BATCH(0);
>+         OUT_BATCH64(0);
>       }
>       OUT_BATCH(SET_FIELD(prog_data->dispatch_grf_start_reg,
>                           GEN7_DS_DISPATCH_START_GRF) |
>diff --git a/src/mesa/drivers/dri/i965/gen8_gs_state.c b/src/mesa/drivers/dri/i965/gen8_gs_state.c
>index 2b74f1bd575..31c6f89bc13 100644
>--- a/src/mesa/drivers/dri/i965/gen8_gs_state.c
>+++ b/src/mesa/drivers/dri/i965/gen8_gs_state.c
>@@ -63,8 +63,7 @@ gen8_upload_gs_state(struct brw_context *brw)
>                      I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
>                      ffs(stage_state->per_thread_scratch) - 11);
>       } else {
>-         OUT_BATCH(0);
>-         OUT_BATCH(0);
>+         OUT_BATCH64(0);
>       }
>
>       /* DW6 */
>diff --git a/src/mesa/drivers/dri/i965/gen8_hs_state.c b/src/mesa/drivers/dri/i965/gen8_hs_state.c
>index ee47e5e54a0..dbdd19b1f5c 100644
>--- a/src/mesa/drivers/dri/i965/gen8_hs_state.c
>+++ b/src/mesa/drivers/dri/i965/gen8_hs_state.c
>@@ -57,8 +57,7 @@ gen8_upload_hs_state(struct brw_context *brw)
>                      I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
>                      ffs(stage_state->per_thread_scratch) - 11);
>       } else {
>-         OUT_BATCH(0);
>-         OUT_BATCH(0);
>+         OUT_BATCH64(0);
>       }
>       OUT_BATCH(GEN7_HS_INCLUDE_VERTEX_HANDLES |
>                 SET_FIELD(prog_data->dispatch_grf_start_reg,
>diff --git a/src/mesa/drivers/dri/i965/gen8_ps_state.c b/src/mesa/drivers/dri/i965/gen8_ps_state.c
>index 03468267ce6..9b1a78c6ee6 100644
>--- a/src/mesa/drivers/dri/i965/gen8_ps_state.c
>+++ b/src/mesa/drivers/dri/i965/gen8_ps_state.c
>@@ -269,8 +269,7 @@ gen8_upload_ps_state(struct brw_context *brw,
>                   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
>                   ffs(stage_state->per_thread_scratch) - 11);
>    } else {
>-      OUT_BATCH(0);
>-      OUT_BATCH(0);
>+      OUT_BATCH64(0);
>    }
>    OUT_BATCH(dw6);
>    OUT_BATCH(dw7);
>diff --git a/src/mesa/drivers/dri/i965/gen8_vs_state.c b/src/mesa/drivers/dri/i965/gen8_vs_state.c
>index 7b66da4b17c..a2b08fe92a0 100644
>--- a/src/mesa/drivers/dri/i965/gen8_vs_state.c
>+++ b/src/mesa/drivers/dri/i965/gen8_vs_state.c
>@@ -62,8 +62,7 @@ upload_vs_state(struct brw_context *brw)
>                   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
>                   ffs(stage_state->per_thread_scratch) - 11);
>    } else {
>-      OUT_BATCH(0);
>-      OUT_BATCH(0);
>+      OUT_BATCH64(0);
>    }
>
>    OUT_BATCH((prog_data->dispatch_grf_start_reg <<
>diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.h b/src/mesa/drivers/dri/i965/intel_batchbuffer.h
>index bf7cadfc4d6..da8f7e561f4 100644
>--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.h
>+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.h
>@@ -161,6 +161,7 @@ intel_batchbuffer_advance(struct brw_context *brw)
>
> #define OUT_BATCH(d) *__map++ = (d)
> #define OUT_BATCH_F(f) OUT_BATCH(float_as_int((f)))
>+#define OUT_BATCH64(d) *((uint64_t *) __map) = (d); __map += 2
> #define OUT_RELOC(buf, read_domains, write_domain, delta) do {    \
>    uint32_t __offset = (__map - brw->batch.map) * 4;              \
>-- 
>2.11.1
>

-- 
Ben Widawsky, Intel Open Source Technology Center