[Mesa-dev] [PATCH 15/16] i965: Check if fast color clear state transition needs sync

[Topi Pohjolainen]

Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
---
 src/mesa/drivers/dri/i965/brw_context.c | 49 +++++++++++++++++++++++++++++++++
 1 file changed, 49 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index 52f8c17..28ed8d1 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -228,6 +228,52 @@ enum intel_write_cache_flush_type {
    INTEL_WRITE_CACHE_SYNC     = 1 << 1,
 };
 
+/*
+ * Check if transition to new fast clear color state requires synchronization:
+ *
+ * Ivybrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
+ *
+ *  Any transition from any value in {Clear, Render, Resolve} to a
+ *  different value in {Clear, Render, Resolve} requires end of pipe
+ *  synchronization.
+ *
+ * On the other hand:
+ *
+ * Ivybrigde PRM Vol 2, Part 1, "11.8 Render Target Fast Clear":
+ *
+ *  After Render target fast clear, pipe-control with color cache write-flush
+ *  must be issued before sending any DRAW commands on that render target
+ *
+ * Empirically it looks that after a clear flushing alone is sufficient while
+ * full sync decreases performance in some benchmarks significantly.
+ */
+static enum intel_write_cache_flush_type
+intel_miptree_fast_clear_needs_sync(const struct brw_context *brw,
+                                    const struct intel_mipmap_tree *mt,
+                                    unsigned level, unsigned layer)
+{
+   if (!mt->mcs_buf || mt->num_samples > 1)
+      return INTEL_WRITE_CACHE_NO_FLUSH;
+
+   /* Presence in the render cache combined with fast clear state of CLEAR
+    * or RESOLVED means that there is fast clear op pending flush and sync.
+    */
+   if (_mesa_set_search(brw->render_cache, mt->bo) == NULL)
+      return INTEL_WRITE_CACHE_NO_FLUSH;
+
+   const enum intel_fast_clear_state curr_state =
+      intel_miptree_get_fast_clear_state(mt, level, layer);
+
+   switch (curr_state) {
+   case INTEL_FAST_CLEAR_STATE_CLEAR:
+      return INTEL_WRITE_CACHE_FLUSH;
+   case INTEL_FAST_CLEAR_STATE_RESOLVED:
+      return INTEL_WRITE_CACHE_SYNC;
+   default:
+      return INTEL_WRITE_CACHE_NO_FLUSH;
+   }
+}
+
 static enum intel_write_cache_flush_type 
 brw_prepare_textures(struct gl_context *ctx)
 {
@@ -381,6 +427,9 @@ brw_prepare_framebuffer(struct gl_context *ctx)
                                          irb->mt_layer, irb->layer_count, 0))
             flush |= INTEL_WRITE_CACHE_SYNC;
       }
+
+      flush |= intel_miptree_fast_clear_needs_sync(
+                  brw, irb->mt, irb->mt_level, irb->mt_layer);
    }
 
    return flush;
-- 
2.5.5