[Mesa-dev] [PATCH 08/10] i965/disasm: Register region formatting

[Toni Lönnberg]

From: "Lonnberg, Toni" <toni.lonnberg at intel.com>

Pre-work for the new shader assembler.

To follow more the style of the documentation and for the shader assembler
parser to be able to handle different styles of register region definitions,
the vertical stride is now delimited differently from the width and horizontal
stride.
---
 src/mesa/drivers/dri/i965/brw_disasm.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c b/src/mesa/drivers/dri/i965/brw_disasm.c
index 44ada00..451ba3f 100644
--- a/src/mesa/drivers/dri/i965/brw_disasm.c
+++ b/src/mesa/drivers/dri/i965/brw_disasm.c
@@ -838,7 +838,7 @@ src_align1_region(FILE *file,
    int err = 0;
    string(file, "<");
    err |= control(file, "vert stride", vert_stride, _vert_stride, NULL);
-   string(file, ",");
+   string(file, ";");
    err |= control(file, "width", width, _width, NULL);
    string(file, ",");
    err |= control(file, "horiz_stride", horiz_stride, _horiz_stride, NULL);
@@ -988,9 +988,9 @@ src0_3src(FILE *file, const struct gen_device_info *devinfo, brw_inst *inst)
    if (src0_subreg_nr || brw_inst_3src_src0_rep_ctrl(devinfo, inst))
       format(file, ".%d", src0_subreg_nr);
    if (brw_inst_3src_src0_rep_ctrl(devinfo, inst))
-      string(file, "<0,1,0>");
+      string(file, "<0;1,0>");
    else {
-      string(file, "<4,4,1>");
+      string(file, "<4;4,1>");
       err |= src_swizzle(file, brw_inst_3src_src0_swizzle(devinfo, inst));
    }
    err |= control(file, "src da16 reg type", three_source_reg_encoding,
@@ -1015,9 +1015,9 @@ src1_3src(FILE *file, const struct gen_device_info *devinfo, brw_inst *inst)
    if (src1_subreg_nr || brw_inst_3src_src1_rep_ctrl(devinfo, inst))
       format(file, ".%d", src1_subreg_nr);
    if (brw_inst_3src_src1_rep_ctrl(devinfo, inst))
-      string(file, "<0,1,0>");
+      string(file, "<0;1,0>");
    else {
-      string(file, "<4,4,1>");
+      string(file, "<4;4,1>");
       err |= src_swizzle(file, brw_inst_3src_src1_swizzle(devinfo, inst));
    }
    err |= control(file, "src da16 reg type", three_source_reg_encoding,
@@ -1043,9 +1043,9 @@ src2_3src(FILE *file, const struct gen_device_info *devinfo, brw_inst *inst)
    if (src2_subreg_nr || brw_inst_3src_src2_rep_ctrl(devinfo, inst))
       format(file, ".%d", src2_subreg_nr);
    if (brw_inst_3src_src2_rep_ctrl(devinfo, inst))
-      string(file, "<0,1,0>");
+      string(file, "<0;1,0>");
    else {
-      string(file, "<4,4,1>");
+      string(file, "<4;4,1>");
       err |= src_swizzle(file, brw_inst_3src_src2_swizzle(devinfo, inst));
    }
    err |= control(file, "src da16 reg type", three_source_reg_encoding,
-- 
2.7.4