[Mesa-dev] [PATCH 06/10] i965/disasm: Immediate value formatting

[Toni Lönnberg]

From: "Lonnberg, Toni" <toni.lonnberg at intel.com>

Pre-work for the new shader assembler.

For the assembler to be able to produce the same bit representation for
immediate values used by disassembled shaders, the disassembly needs to output
the values as hexadecimals. To remove any ambiguity between the value and the
type, it also needs to be delimited.
---
 src/mesa/drivers/dri/i965/brw_disasm.c | 51 +++++++++++++++++++++++++---------
 1 file changed, 38 insertions(+), 13 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c b/src/mesa/drivers/dri/i965/brw_disasm.c
index ec788c6..1bae2cd 100644
--- a/src/mesa/drivers/dri/i965/brw_disasm.c
+++ b/src/mesa/drivers/dri/i965/brw_disasm.c
@@ -1056,37 +1056,62 @@ src2_3src(FILE *file, const struct gen_device_info *devinfo, brw_inst *inst)
 static int
 imm(FILE *file, const struct gen_device_info *devinfo, unsigned type, brw_inst *inst)
 {
+   bool disasm = (INTEL_DEBUG & DEBUG_DISASM) != 0;
+
    switch (type) {
    case BRW_HW_REG_TYPE_UD:
-      format(file, "0x%08xUD", brw_inst_imm_ud(devinfo, inst));
+      format(file, "0x%08x:UD", brw_inst_imm_ud(devinfo, inst));
       break;
    case BRW_HW_REG_TYPE_D:
-      format(file, "%dD", brw_inst_imm_d(devinfo, inst));
+      format(file, "%d:D", brw_inst_imm_d(devinfo, inst));
       break;
    case BRW_HW_REG_TYPE_UW:
-      format(file, "0x%04xUW", (uint16_t) brw_inst_imm_ud(devinfo, inst));
+      format(file, "0x%04x:UW", (uint16_t) brw_inst_imm_ud(devinfo, inst));
       break;
    case BRW_HW_REG_TYPE_W:
-      format(file, "%dW", (int16_t) brw_inst_imm_d(devinfo, inst));
+      format(file, "%d:W", (int16_t) brw_inst_imm_d(devinfo, inst));
       break;
    case BRW_HW_REG_IMM_TYPE_UV:
-      format(file, "0x%08xUV", brw_inst_imm_ud(devinfo, inst));
+      format(file, "0x%08x:UV", brw_inst_imm_ud(devinfo, inst));
       break;
    case BRW_HW_REG_IMM_TYPE_VF:
-      format(file, "[%-gF, %-gF, %-gF, %-gF]VF",
-             brw_vf_to_float(brw_inst_imm_ud(devinfo, inst)),
-             brw_vf_to_float(brw_inst_imm_ud(devinfo, inst) >> 8),
-             brw_vf_to_float(brw_inst_imm_ud(devinfo, inst) >> 16),
-             brw_vf_to_float(brw_inst_imm_ud(devinfo, inst) >> 24));
+      if (disasm) {
+         format(file, "0x%08x:VF", brw_inst_imm_ud(devinfo, inst));
+      } else {
+         format(file, "[%-gF, %-gF, %-gF, %-gF]:VF",
+                brw_vf_to_float(brw_inst_imm_ud(devinfo, inst)),
+                brw_vf_to_float(brw_inst_imm_ud(devinfo, inst) >> 8),
+                brw_vf_to_float(brw_inst_imm_ud(devinfo, inst) >> 16),
+                brw_vf_to_float(brw_inst_imm_ud(devinfo, inst) >> 24));
+      }
       break;
    case BRW_HW_REG_IMM_TYPE_V:
-      format(file, "0x%08xV", brw_inst_imm_ud(devinfo, inst));
+      format(file, "0x%08x:V", brw_inst_imm_ud(devinfo, inst));
       break;
    case BRW_HW_REG_TYPE_F:
-      format(file, "%-gF", brw_inst_imm_f(devinfo, inst));
+      if (disasm) {
+         union {
+            float f;
+            unsigned u;
+         } dt;
+         dt.f = brw_inst_imm_f(devinfo, inst);
+         format(file, "0x%08x:F", dt.u);
+      } else {
+         format(file, "%-g:F", brw_inst_imm_f(devinfo, inst));
+      }
       break;
    case GEN8_HW_REG_IMM_TYPE_DF:
-      format(file, "%-gDF", brw_inst_imm_df(devinfo, inst));
+      if (disasm)
+      {
+         union {
+            double d;
+            uint64_t u;
+         } dt;
+         dt.d = brw_inst_imm_df(devinfo, inst);
+         format(file, "0x%016"PRIx64":DF", dt.u);
+      } else {
+         format(file, "%-g:DF", brw_inst_imm_df(devinfo, inst));
+      }
       break;
    case GEN8_HW_REG_IMM_TYPE_HF:
       string(file, "Half Float IMM");
-- 
2.7.4