[Mesa-dev] [PATCH 4/5] anv: Pull all clflushing into a clflush_range helper
Jason Ekstrand
jason at jlekstrand.net
Mon Feb 20 19:21:58 UTC 2017
All this cache line address calculation stuff is tricky. Let's not
duplicate it more places than we have to.
---
src/intel/vulkan/anv_device.c | 15 ++++-----------
src/intel/vulkan/anv_private.h | 18 +++++++++---------
2 files changed, 13 insertions(+), 20 deletions(-)
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index c8277cb..258a25f 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -1487,18 +1487,11 @@ clflush_mapped_ranges(struct anv_device *device,
{
for (uint32_t i = 0; i < count; i++) {
ANV_FROM_HANDLE(anv_device_memory, mem, ranges[i].memory);
- void *p = mem->map + (ranges[i].offset & ~CACHELINE_MASK);
- void *end;
+ if (ranges[i].offset >= mem->map_size)
+ continue;
- if (ranges[i].offset + ranges[i].size > mem->map_size)
- end = mem->map + mem->map_size;
- else
- end = mem->map + ranges[i].offset + ranges[i].size;
-
- while (p < end) {
- __builtin_ia32_clflush(p);
- p += CACHELINE_SIZE;
- }
+ anv_clflush_range(mem->map + ranges[i].offset,
+ MIN2(ranges[i].size, mem->map_size - ranges[i].offset));
}
}
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index 73a3f29..39b1235 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -440,12 +440,11 @@ struct anv_state_stream {
#define CACHELINE_MASK 63
static inline void
-anv_flush_range(void *start, size_t size)
+anv_clflush_range(void *start, size_t size)
{
void *p = (void *) (((uintptr_t) start) & ~CACHELINE_MASK);
void *end = start + size;
- __builtin_ia32_mfence();
while (p < end) {
__builtin_ia32_clflush(p);
p += CACHELINE_SIZE;
@@ -453,15 +452,16 @@ anv_flush_range(void *start, size_t size)
}
static inline void
-anv_invalidate_range(void *start, size_t size)
+anv_flush_range(void *start, size_t size)
{
- void *p = (void *) (((uintptr_t) start) & ~CACHELINE_MASK);
- void *end = start + size;
+ __builtin_ia32_mfence();
+ anv_clflush_range(start, size);
+}
- while (p < end) {
- __builtin_ia32_clflush(p);
- p += CACHELINE_SIZE;
- }
+static inline void
+anv_invalidate_range(void *start, size_t size)
+{
+ anv_clflush_range(start, size);
__builtin_ia32_mfence();
}
--
2.5.0.400.gff86faf
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