[Mesa-dev] [PATCH mesa 3/5] gallium/docs: add missing newlines
Eric Engestrom
eric.engestrom at imgtec.com
Tue Feb 21 14:15:37 UTC 2017
Without these, mathjax considers these as the continuation of the
previous line.
Signed-off-by: Eric Engestrom <eric.engestrom at imgtec.com>
---
src/gallium/docs/source/tgsi.rst | 33 +++++++++++++++++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/src/gallium/docs/source/tgsi.rst b/src/gallium/docs/source/tgsi.rst
index b9b9d6ca34..de73e5291a 100644
--- a/src/gallium/docs/source/tgsi.rst
+++ b/src/gallium/docs/source/tgsi.rst
@@ -1806,6 +1806,7 @@ two-component vectors with doubled precision in each component.
.. math::
dst.xy = |src0.xy|
+
dst.zw = |src0.zw|
.. opcode:: DADD - Add
@@ -2060,6 +2061,7 @@ two-component vectors with 64-bits in each component.
.. math::
dst.xy = |src0.xy|
+
dst.zw = |src0.zw|
.. opcode:: I64NEG - 64-bit Integer Negate
@@ -2069,6 +2071,7 @@ two-component vectors with 64-bits in each component.
.. math::
dst.xy = -src.xy
+
dst.zw = -src.zw
.. opcode:: I64SSG - 64-bit Integer Set Sign
@@ -2076,6 +2079,7 @@ two-component vectors with 64-bits in each component.
.. math::
dst.xy = (src0.xy < 0) ? -1 : (src0.xy > 0) ? 1 : 0
+
dst.zw = (src0.zw < 0) ? -1 : (src0.zw > 0) ? 1 : 0
.. opcode:: U64ADD - 64-bit Integer Add
@@ -2083,6 +2087,7 @@ two-component vectors with 64-bits in each component.
.. math::
dst.xy = src0.xy + src1.xy
+
dst.zw = src0.zw + src1.zw
.. opcode:: U64MUL - 64-bit Integer Multiply
@@ -2090,6 +2095,7 @@ two-component vectors with 64-bits in each component.
.. math::
dst.xy = src0.xy * src1.xy
+
dst.zw = src0.zw * src1.zw
.. opcode:: U64SEQ - 64-bit Integer Set on Equal
@@ -2097,6 +2103,7 @@ two-component vectors with 64-bits in each component.
.. math::
dst.x = src0.xy == src1.xy ? \sim 0 : 0
+
dst.z = src0.zw == src1.zw ? \sim 0 : 0
.. opcode:: U64SNE - 64-bit Integer Set on Not Equal
@@ -2104,6 +2111,7 @@ two-component vectors with 64-bits in each component.
.. math::
dst.x = src0.xy != src1.xy ? \sim 0 : 0
+
dst.z = src0.zw != src1.zw ? \sim 0 : 0
.. opcode:: U64SLT - 64-bit Unsigned Integer Set on Less Than
@@ -2111,6 +2119,7 @@ two-component vectors with 64-bits in each component.
.. math::
dst.x = src0.xy < src1.xy ? \sim 0 : 0
+
dst.z = src0.zw < src1.zw ? \sim 0 : 0
.. opcode:: U64SGE - 64-bit Unsigned Integer Set on Greater Equal
@@ -2118,6 +2127,7 @@ two-component vectors with 64-bits in each component.
.. math::
dst.x = src0.xy >= src1.xy ? \sim 0 : 0
+
dst.z = src0.zw >= src1.zw ? \sim 0 : 0
.. opcode:: I64SLT - 64-bit Signed Integer Set on Less Than
@@ -2125,6 +2135,7 @@ two-component vectors with 64-bits in each component.
.. math::
dst.x = src0.xy < src1.xy ? \sim 0 : 0
+
dst.z = src0.zw < src1.zw ? \sim 0 : 0
.. opcode:: I64SGE - 64-bit Signed Integer Set on Greater Equal
@@ -2132,6 +2143,7 @@ two-component vectors with 64-bits in each component.
.. math::
dst.x = src0.xy >= src1.xy ? \sim 0 : 0
+
dst.z = src0.zw >= src1.zw ? \sim 0 : 0
.. opcode:: I64MIN - Minimum of 64-bit Signed Integers
@@ -2139,6 +2151,7 @@ two-component vectors with 64-bits in each component.
.. math::
dst.xy = min(src0.xy, src1.xy)
+
dst.zw = min(src0.zw, src1.zw)
.. opcode:: U64MIN - Minimum of 64-bit Unsigned Integers
@@ -2146,6 +2159,7 @@ two-component vectors with 64-bits in each component.
.. math::
dst.xy = min(src0.xy, src1.xy)
+
dst.zw = min(src0.zw, src1.zw)
.. opcode:: I64MAX - Maximum of 64-bit Signed Integers
@@ -2153,6 +2167,7 @@ two-component vectors with 64-bits in each component.
.. math::
dst.xy = max(src0.xy, src1.xy)
+
dst.zw = max(src0.zw, src1.zw)
.. opcode:: U64MAX - Maximum of 64-bit Unsigned Integers
@@ -2160,6 +2175,7 @@ two-component vectors with 64-bits in each component.
.. math::
dst.xy = max(src0.xy, src1.xy)
+
dst.zw = max(src0.zw, src1.zw)
.. opcode:: U64SHL - Shift Left 64-bit Unsigned Integer
@@ -2169,6 +2185,7 @@ two-component vectors with 64-bits in each component.
.. math::
dst.xy = src0.xy << (0x3f \& src1.x)
+
dst.zw = src0.zw << (0x3f \& src1.y)
.. opcode:: I64SHR - Arithmetic Shift Right (of 64-bit Signed Integer)
@@ -2178,6 +2195,7 @@ two-component vectors with 64-bits in each component.
.. math::
dst.xy = src0.xy >> (0x3f \& src1.x)
+
dst.zw = src0.zw >> (0x3f \& src1.y)
.. opcode:: U64SHR - Logical Shift Right (of 64-bit Unsigned Integer)
@@ -2187,6 +2205,7 @@ two-component vectors with 64-bits in each component.
.. math::
dst.xy = src0.xy >> (unsigned) (0x3f \& src1.x)
+
dst.zw = src0.zw >> (unsigned) (0x3f \& src1.y)
.. opcode:: I64DIV - 64-bit Signed Integer Division
@@ -2194,6 +2213,7 @@ two-component vectors with 64-bits in each component.
.. math::
dst.xy = src0.xy \ src1.xy
+
dst.zw = src0.zw \ src1.zw
.. opcode:: U64DIV - 64-bit Unsigned Integer Division
@@ -2201,6 +2221,7 @@ two-component vectors with 64-bits in each component.
.. math::
dst.xy = src0.xy \ src1.xy
+
dst.zw = src0.zw \ src1.zw
.. opcode:: U64MOD - 64-bit Unsigned Integer Remainder
@@ -2208,6 +2229,7 @@ two-component vectors with 64-bits in each component.
.. math::
dst.xy = src0.xy \bmod src1.xy
+
dst.zw = src0.zw \bmod src1.zw
.. opcode:: I64MOD - 64-bit Signed Integer Remainder
@@ -2215,6 +2237,7 @@ two-component vectors with 64-bits in each component.
.. math::
dst.xy = src0.xy \bmod src1.xy
+
dst.zw = src0.zw \bmod src1.zw
.. opcode:: F2U64 - Float to 64-bit Unsigned Int
@@ -2222,6 +2245,7 @@ two-component vectors with 64-bits in each component.
.. math::
dst.xy = (uint64_t) src0.x
+
dst.zw = (uint64_t) src0.y
.. opcode:: F2I64 - Float to 64-bit Int
@@ -2229,6 +2253,7 @@ two-component vectors with 64-bits in each component.
.. math::
dst.xy = (int64_t) src0.x
+
dst.zw = (int64_t) src0.y
.. opcode:: U2I64 - Unsigned Integer to 64-bit Integer
@@ -2238,6 +2263,7 @@ two-component vectors with 64-bits in each component.
.. math::
dst.xy = (uint64_t) src0.x
+
dst.zw = (uint64_t) src0.y
.. opcode:: I2I64 - Signed Integer to 64-bit Integer
@@ -2247,6 +2273,7 @@ two-component vectors with 64-bits in each component.
.. math::
dst.xy = (int64_t) src0.x
+
dst.zw = (int64_t) src0.y
.. opcode:: D2U64 - Double to 64-bit Unsigned Int
@@ -2254,6 +2281,7 @@ two-component vectors with 64-bits in each component.
.. math::
dst.xy = (uint64_t) src0.xy
+
dst.zw = (uint64_t) src0.zw
.. opcode:: D2I64 - Double to 64-bit Int
@@ -2261,6 +2289,7 @@ two-component vectors with 64-bits in each component.
.. math::
dst.xy = (int64_t) src0.xy
+
dst.zw = (int64_t) src0.zw
.. opcode:: U642F - 64-bit unsigned integer to float
@@ -2268,6 +2297,7 @@ two-component vectors with 64-bits in each component.
.. math::
dst.x = (float) src0.xy
+
dst.y = (float) src0.zw
.. opcode:: I642F - 64-bit Int to Float
@@ -2275,6 +2305,7 @@ two-component vectors with 64-bits in each component.
.. math::
dst.x = (float) src0.xy
+
dst.y = (float) src0.zw
.. opcode:: U642D - 64-bit unsigned integer to double
@@ -2282,6 +2313,7 @@ two-component vectors with 64-bits in each component.
.. math::
dst.xy = (double) src0.xy
+
dst.zw = (double) src0.zw
.. opcode:: I642D - 64-bit Int to double
@@ -2289,6 +2321,7 @@ two-component vectors with 64-bits in each component.
.. math::
dst.xy = (double) src0.xy
+
dst.zw = (double) src0.zw
.. _samplingopcodes:
--
Cheers,
Eric
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