[Mesa-dev] [PATCH 17/24] radeonsi: enable TC L2 for tessellation offchip stores

[Marek Olšák]

From: Marek Olšák <marek.olsak at amd.com>

Vulkan does the same thing.
---
 src/gallium/drivers/radeonsi/si_shader.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c
index daaf9f1..71b5b7a 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -1042,29 +1042,29 @@ static void store_output_tcs(struct lp_build_tgsi_context *bld_base,
 		/* Skip LDS stores if there is no LDS read of this output. */
 		if (!skip_lds_store)
 			lds_store(bld_base, chan_index, dw_addr, value);
 
 		value = LLVMBuildBitCast(gallivm->builder, value, ctx->i32, "");
 		values[chan_index] = value;
 
 		if (inst->Dst[0].Register.WriteMask != 0xF && !is_tess_factor) {
 			ac_build_buffer_store_dword(&ctx->ac, buffer, value, 1,
 						    buf_addr, base,
-						    4 * chan_index, 1, 1, 1);
+						    4 * chan_index, 1, 1, 0);
 		}
 	}
 
 	if (inst->Dst[0].Register.WriteMask == 0xF && !is_tess_factor) {
 		LLVMValueRef value = lp_build_gather_values(bld_base->base.gallivm,
 		                                            values, 4);
 		ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buf_addr,
-					    base, 0, 1, 1, 1);
+					    base, 0, 1, 1, 0);
 	}
 }
 
 static LLVMValueRef fetch_input_gs(
 	struct lp_build_tgsi_context *bld_base,
 	const struct tgsi_full_src_register *reg,
 	enum tgsi_opcode_type type,
 	unsigned swizzle)
 {
 	struct lp_build_context *base = &bld_base->base;
@@ -2405,21 +2405,21 @@ static void si_copy_tcs_inputs(struct lp_build_tgsi_context *bld_base)
 
 		LLVMValueRef buffer_addr = get_tcs_tes_buffer_address(ctx,
 					      get_rel_patch_id(ctx),
 		                              invocation_id,
 		                              lp_build_const_int32(gallivm, i));
 
 		LLVMValueRef value = lds_load(bld_base, TGSI_TYPE_SIGNED, ~0,
 		                              lds_ptr);
 
 		ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buffer_addr,
-					    buffer_offset, 0, 1, 1, 1);
+					    buffer_offset, 0, 1, 1, 0);
 	}
 }
 
 static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
 				  LLVMValueRef rel_patch_id,
 				  LLVMValueRef invocation_id,
 				  LLVMValueRef tcs_out_current_patch_data_offset)
 {
 	struct si_shader_context *ctx = si_shader_context(bld_base);
 	struct gallivm_state *gallivm = bld_base->base.gallivm;
@@ -2520,32 +2520,32 @@ static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
 				  lp_build_const_int32(gallivm, 4 * stride), "");
 
 	lp_build_if(&inner_if_ctx, gallivm,
 		    LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
 				  rel_patch_id, bld_base->uint_bld.zero, ""));
 
 	/* Store the dynamic HS control word. */
 	ac_build_buffer_store_dword(&ctx->ac, buffer,
 				    lp_build_const_int32(gallivm, 0x80000000),
 				    1, lp_build_const_int32(gallivm, 0), tf_base,
-				    0, 1, 1, 1);
+				    0, 1, 1, 0);
 
 	lp_build_endif(&inner_if_ctx);
 
 	/* Store the tessellation factors. */
 	ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
 				    MIN2(stride, 4), byteoffset, tf_base,
-				    4, 1, 1, 1);
+				    4, 1, 1, 0);
 	if (vec1)
 		ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
 					    stride - 4, byteoffset, tf_base,
-					    20, 1, 1, 1);
+					    20, 1, 1, 0);
 
 	/* Store the tess factors into the offchip buffer if TES reads them. */
 	if (shader->key.part.tcs.epilog.tes_reads_tess_factors) {
 		LLVMValueRef buf, base, inner_vec, outer_vec, tf_outer_offset;
 		LLVMValueRef tf_inner_offset;
 		unsigned param_outer, param_inner;
 
 		buf = ac_build_indexed_load_const(&ctx->ac, rw_buffers,
 				LLVMConstInt(ctx->i32, SI_HS_RING_TESS_OFFCHIP, 0));
 		base = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
@@ -2553,32 +2553,32 @@ static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
 		param_outer = si_shader_io_get_unique_index(
 				      TGSI_SEMANTIC_TESSOUTER, 0);
 		tf_outer_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
 					LLVMConstInt(ctx->i32, param_outer, 0));
 
 		outer_vec = lp_build_gather_values(gallivm, outer,
 						   util_next_power_of_two(outer_comps));
 
 		ac_build_buffer_store_dword(&ctx->ac, buf, outer_vec,
 					    outer_comps, tf_outer_offset,
-					    base, 0, 1, 1, 1);
+					    base, 0, 1, 1, 0);
 		if (inner_comps) {
 			param_inner = si_shader_io_get_unique_index(
 					      TGSI_SEMANTIC_TESSINNER, 0);
 			tf_inner_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
 					LLVMConstInt(ctx->i32, param_inner, 0));
 
 			inner_vec = inner_comps == 1 ? inner[0] :
 				    lp_build_gather_values(gallivm, inner, inner_comps);
 			ac_build_buffer_store_dword(&ctx->ac, buf, inner_vec,
 						    inner_comps, tf_inner_offset,
-						    base, 0, 1, 1, 1);
+						    base, 0, 1, 1, 0);
 		}
 	}
 
 	lp_build_endif(&if_ctx);
 }
 
 /* This only writes the tessellation factor levels. */
 static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context *bld_base)
 {
 	struct si_shader_context *ctx = si_shader_context(bld_base);
-- 
2.7.4