[Mesa-dev] [PATCH v2 65/73] ac/nir, radv: move force_persample to ac_shader_info::force_persample

Nicolai Hähnle nhaehnle at gmail.com
Wed Jul 5 10:48:49 UTC 2017


From: Nicolai Hähnle <nicolai.haehnle at amd.com>

Avoid accessing radv-specific structures during the meat of NIR-to-LLVM
translation.
---
 src/amd/common/ac_nir_to_llvm.c  | 4 +---
 src/amd/common/ac_nir_to_llvm.h  | 1 -
 src/amd/common/ac_shader_info.c  | 6 ++++++
 src/amd/common/ac_shader_info.h  | 1 +
 src/amd/vulkan/radv_cmd_buffer.c | 2 +-
 src/amd/vulkan/radv_pipeline.c   | 2 +-
 6 files changed, 10 insertions(+), 6 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index b1d13d8..6ba03cf 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -3970,25 +3970,23 @@ static void visit_intrinsic(struct ac_nir_context *ctx,
 		} else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
 			ctx->nctx->shader_info->tcs.uses_prim_id = true;
 			result = ctx->nctx->tcs_patch_id;
 		} else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
 			ctx->nctx->shader_info->tcs.uses_prim_id = true;
 			result = ctx->nctx->tes_patch_id;
 		} else
 			fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
 		break;
 	case nir_intrinsic_load_sample_id:
-		ctx->nctx->shader_info->fs.force_persample = true;
 		result = unpack_param(ctx->nctx, ctx->nctx->ancillary, 8, 4);
 		break;
 	case nir_intrinsic_load_sample_pos:
-		ctx->nctx->shader_info->fs.force_persample = true;
 		result = load_sample_pos(ctx->nctx);
 		break;
 	case nir_intrinsic_load_sample_mask_in:
 		result = ctx->nctx->sample_coverage;
 		break;
 	case nir_intrinsic_load_front_face:
 		result = ctx->abi->front_face;
 		break;
 	case nir_intrinsic_load_instance_id:
 		result = ctx->abi->instance_id;
@@ -4927,21 +4925,21 @@ handle_fs_input_decl(struct nir_to_llvm_context *ctx,
 	unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
 	LLVMValueRef interp;
 
 	variable->data.driver_location = idx * 4;
 	ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
 
 	if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
 		unsigned interp_type;
 		if (variable->data.sample) {
 			interp_type = INTERP_SAMPLE;
-			ctx->shader_info->fs.force_persample = true;
+			ctx->shader_info->info.ps.force_persample = true;
 		} else if (variable->data.centroid)
 			interp_type = INTERP_CENTROID;
 		else
 			interp_type = INTERP_CENTER;
 
 		interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
 	} else
 		interp = NULL;
 
 	for (unsigned i = 0; i < attrib_count; ++i)
diff --git a/src/amd/common/ac_nir_to_llvm.h b/src/amd/common/ac_nir_to_llvm.h
index 0cb48a8..7def4b7 100644
--- a/src/amd/common/ac_nir_to_llvm.h
+++ b/src/amd/common/ac_nir_to_llvm.h
@@ -162,21 +162,20 @@ struct ac_shader_variant_info {
 			uint32_t input_mask;
 			unsigned output_mask;
 			uint32_t flat_shaded_mask;
 			bool has_pcoord;
 			bool can_discard;
 			bool writes_z;
 			bool writes_stencil;
 			bool writes_sample_mask;
 			bool early_fragment_test;
 			bool writes_memory;
-			bool force_persample;
 			bool prim_id_input;
 			bool layer_input;
 		} fs;
 		struct {
 			unsigned block_size[3];
 		} cs;
 		struct {
 			unsigned vertices_in;
 			unsigned vertices_out;
 			unsigned output_prim;
diff --git a/src/amd/common/ac_shader_info.c b/src/amd/common/ac_shader_info.c
index 7d34535..8668c4c 100644
--- a/src/amd/common/ac_shader_info.c
+++ b/src/amd/common/ac_shader_info.c
@@ -38,20 +38,26 @@ gather_intrinsic_info(nir_intrinsic_instr *instr, struct ac_shader_info *info)
 		break;
 	case nir_intrinsic_load_draw_id:
 		info->vs.needs_draw_id = true;
 		break;
 	case nir_intrinsic_load_instance_id:
 		info->vs.needs_instance_id = true;
 		break;
 	case nir_intrinsic_load_num_work_groups:
 		info->cs.grid_components_used = instr->num_components;
 		break;
+	case nir_intrinsic_load_sample_id:
+		info->ps.force_persample = true;
+		break;
+	case nir_intrinsic_load_sample_pos:
+		info->ps.force_persample = true;
+		break;
 	case nir_intrinsic_vulkan_resource_index:
 		info->desc_set_used_mask |= (1 << nir_intrinsic_desc_set(instr));
 		break;
 	case nir_intrinsic_image_load:
 	case nir_intrinsic_image_store:
 	case nir_intrinsic_image_atomic_add:
 	case nir_intrinsic_image_atomic_min:
 	case nir_intrinsic_image_atomic_max:
 	case nir_intrinsic_image_atomic_and:
 	case nir_intrinsic_image_atomic_or:
diff --git a/src/amd/common/ac_shader_info.h b/src/amd/common/ac_shader_info.h
index 5bc16cc..965ad54 100644
--- a/src/amd/common/ac_shader_info.h
+++ b/src/amd/common/ac_shader_info.h
@@ -29,20 +29,21 @@ struct ac_nir_compiler_options;
 
 struct ac_shader_info {
 	bool needs_push_constants;
 	uint32_t desc_set_used_mask;
 	struct {
 		bool has_vertex_buffers; /* needs vertex buffers and base/start */
 		bool needs_draw_id;
 		bool needs_instance_id;
 	} vs;
 	struct {
+		bool force_persample;
 		bool needs_sample_positions;
 	} ps;
 	struct {
 		uint8_t grid_components_used;
 	} cs;
 };
 
 /* A NIR pass to gather all the info needed to optimise the allocation patterns
  * for the RADV user sgprs
  */
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 105384d..2a209bc 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -829,21 +829,21 @@ radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
 
 	radeon_set_context_reg(cmd_buffer->cs, R_02880C_DB_SHADER_CONTROL,
 			       pipeline->graphics.db_shader_control);
 
 	radeon_set_context_reg(cmd_buffer->cs, R_0286CC_SPI_PS_INPUT_ENA,
 			       ps->config.spi_ps_input_ena);
 
 	radeon_set_context_reg(cmd_buffer->cs, R_0286D0_SPI_PS_INPUT_ADDR,
 			       ps->config.spi_ps_input_addr);
 
-	if (ps->info.fs.force_persample)
+	if (ps->info.info.ps.force_persample)
 		spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
 
 	radeon_set_context_reg(cmd_buffer->cs, R_0286D8_SPI_PS_IN_CONTROL,
 			       S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
 
 	radeon_set_context_reg(cmd_buffer->cs, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
 
 	radeon_set_context_reg(cmd_buffer->cs, R_028710_SPI_SHADER_Z_FORMAT,
 			       pipeline->graphics.shader_z_format);
 
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 49610a1..6e4afd3 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1315,21 +1315,21 @@ radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
 	struct radv_multisample_state *ms = &pipeline->graphics.ms;
 	unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
 	int ps_iter_samples = 1;
 	uint32_t mask = 0xffff;
 
 	if (vkms)
 		ms->num_samples = vkms->rasterizationSamples;
 	else
 		ms->num_samples = 1;
 
-	if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.force_persample) {
+	if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.force_persample) {
 		ps_iter_samples = ms->num_samples;
 	}
 
 	ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
 	ms->pa_sc_aa_config = 0;
 	ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
 		S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
 	ms->pa_sc_mode_cntl_1 =
 		S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
 		S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
-- 
2.9.3



More information about the mesa-dev mailing list