[Mesa-dev] [PATCH v3 02/14] i965/miptree: Allocate HiZ up-front

[Jason Ekstrand]

HiZ, like MCS and CCS_E, can compress more than just clear colors so we
want it turned on whenever the miptree is being used as a depth
attachment.  It's theoretically possible for someone to create a depth
texture, upload data with glTexSubImage2D, and texture from it without
ever binding it as a depth target.  If this happens, we would end up
wasting a bit of space by allocating a HiZ surface we never use.
However, this is rather unlikely out side of test cases, so we're better
off just allocating it up-front.
---
 src/mesa/drivers/dri/i965/intel_fbo.c         |  6 ------
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 17 ++++++-----------
 2 files changed, 6 insertions(+), 17 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c b/src/mesa/drivers/dri/i965/intel_fbo.c
index 03427e8..91d75ed 100644
--- a/src/mesa/drivers/dri/i965/intel_fbo.c
+++ b/src/mesa/drivers/dri/i965/intel_fbo.c
@@ -556,12 +556,6 @@ intel_renderbuffer_update_wrapper(struct brw_context *brw,
 
    intel_renderbuffer_set_draw_offset(irb);
 
-   if (mt->aux_usage == ISL_AUX_USAGE_HIZ && !mt->hiz_buf) {
-      intel_miptree_alloc_hiz(brw, mt);
-      if (!mt->hiz_buf)
-	 return false;
-   }
-
    return true;
 }
 
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 12b8d04..f0b93d5 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -1180,7 +1180,6 @@ intel_miptree_create_for_renderbuffer(struct brw_context *brw,
 {
    struct intel_mipmap_tree *mt;
    uint32_t depth = 1;
-   bool ok;
    GLenum target = num_samples > 1 ? GL_TEXTURE_2D_MULTISAMPLE : GL_TEXTURE_2D;
    const uint32_t layout_flags = MIPTREE_LAYOUT_ACCELERATED_UPLOAD |
                                  MIPTREE_LAYOUT_TILING_ANY |
@@ -1192,12 +1191,6 @@ intel_miptree_create_for_renderbuffer(struct brw_context *brw,
    if (!mt)
       goto fail;
 
-   if (mt->aux_usage == ISL_AUX_USAGE_HIZ) {
-      ok = intel_miptree_alloc_hiz(brw, mt);
-      if (!ok)
-         goto fail;
-   }
-
    return mt;
 
 fail:
@@ -1983,9 +1976,9 @@ intel_miptree_alloc_hiz(struct brw_context *brw,
 /**
  * Allocate the initial aux surface for a miptree based on mt->aux_usage
  *
- * Since MCS and CCS_E can compress more than just clear color, we create the
- * auxiliary surfaces up-front.  CCS_D, on the other hand, can only compress
- * clear color so we wait until an actual fast-clear to allocate it.
+ * Since MCS, HiZ, and CCS_E can compress more than just clear color, we
+ * create the auxiliary surfaces up-front.  CCS_D, on the other hand, can only
+ * compress clear color so we wait until an actual fast-clear to allocate it.
  */
 static bool
 intel_miptree_alloc_aux(struct brw_context *brw,
@@ -1996,7 +1989,9 @@ intel_miptree_alloc_aux(struct brw_context *brw,
       return true;
 
    case ISL_AUX_USAGE_HIZ:
-      /* HiZ gets allocated elsewhere for no good reason. */
+      assert(!_mesa_is_format_color_format(mt->format));
+      if (!intel_miptree_alloc_hiz(brw, mt))
+         return false;
       return true;
 
    case ISL_AUX_USAGE_MCS:
-- 
2.5.0.400.gff86faf