[Mesa-dev] [PATCH 21/45] i965: Add support for control register

[Alejandro Piñeiro]

From: Jose Maria Casanova Crespo <jmcasanova at igalia.com>

Control register cr0 in i965 can be used to change the rounding modes
in 32-bit to 16-bit floating-point conversions.

>From intel Skylake PRM, vol 07, section "Register and Tegister Regions",
 subsection "Control Register" (page 754):

"Subregister cr0.0:ud contains normal operation control fields such as the
 floating-point mode ... "

Floating-point Rounding mode is changed at bits 5:4 of cr0.0:

"Rounding Mode. This field specifies the FPU rounding mode. It is
initialized by Thread Dispatch."
  00b = Round to Nearest or Even (RTNE)
  01b = Round Up, toward +inf (RU)
  10b = Round Down, toward -inf (RD)
  11b = Round Toward Zero (RTZ)"
---
 src/intel/compiler/brw_reg.h | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/src/intel/compiler/brw_reg.h b/src/intel/compiler/brw_reg.h
index 17a51fb..6355e3f 100644
--- a/src/intel/compiler/brw_reg.h
+++ b/src/intel/compiler/brw_reg.h
@@ -842,6 +842,12 @@ brw_notification_reg(void)
 }
 
 static inline struct brw_reg
+brw_cr0_reg(unsigned subnr)
+{
+   return brw_ud1_reg(BRW_ARCHITECTURE_REGISTER_FILE, BRW_ARF_CONTROL, subnr);
+}
+
+static inline struct brw_reg
 brw_sr0_reg(unsigned subnr)
 {
    return brw_ud1_reg(BRW_ARCHITECTURE_REGISTER_FILE, BRW_ARF_STATE, subnr);
-- 
2.9.3