[Mesa-dev] [PATCH 40/45] i965/fs: 16-bit source payloads always use 1 register

[Alejandro Piñeiro]

From: Jose Maria Casanova Crespo <jmcasanova at igalia.com>

Render Target Message's payloads for 16bit values fit in only one
register.

>From Intel PRM vol07, page 249 "Render Target Messages" / "Message
Data Payloads"

   "The half precision Render Target Write messages have data payloads
    that can pack a full SIMD16 payload into 1 register instead of
    two. The half-precision packed format is used for RGBA and Source
    0 Alpha, but Source Depth data payload is always supplied in full
    precision."

So when 16-bit data is uploaded to the payload it will use 1 register
independently of it is SIMD16 or SIMD8.
---
 src/intel/compiler/brw_fs.cpp | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index 8de6730..69ee66b 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -3384,7 +3384,10 @@ fs_visitor::lower_load_payload()
       for (uint8_t i = inst->header_size; i < inst->sources; i++) {
          if (inst->src[i].file != BAD_FILE)
             ibld.MOV(retype(dst, inst->src[i].type), inst->src[i]);
-         dst = offset(dst, ibld, 1);
+         if (type_sz(inst->src[i].type) == 2)
+            dst = byte_offset(dst, REG_SIZE);
+         else
+            dst = offset(dst, ibld, 1);
       }
 
       inst->remove(block);
-- 
2.9.3