[Mesa-dev] [PATCH 14/20] i965/fs: Implement ARB_shader_ballot operations

[Kenneth Graunke]

On Thursday, July 6, 2017 4:48:24 PM PDT Matt Turner wrote:
> ---
>  src/intel/compiler/brw_fs_nir.cpp | 41 +++++++++++++++++++++++++++++++++++++++
>  src/intel/compiler/brw_nir.c      |  1 +
>  2 files changed, 42 insertions(+)
> 
> diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp
> index 17f35e081d..25e9b703eb 100644
> --- a/src/intel/compiler/brw_fs_nir.cpp
> +++ b/src/intel/compiler/brw_fs_nir.cpp
> @@ -4075,6 +4075,10 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
>        break;
>     }
>  
> +   case nir_intrinsic_load_subgroup_size:
> +      bld.MOV(retype(dest, BRW_REGISTER_TYPE_D), brw_imm_d(dispatch_width));
> +      break;
> +
>     case nir_intrinsic_load_subgroup_invocation: {
>        fs_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_UW);
>        dest = retype(dest, BRW_REGISTER_TYPE_UD);
> @@ -4090,6 +4094,13 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
>        break;
>     }
>  
> +   case nir_intrinsic_load_subgroup_eq_mask:
> +   case nir_intrinsic_load_subgroup_ge_mask:
> +   case nir_intrinsic_load_subgroup_gt_mask:
> +   case nir_intrinsic_load_subgroup_le_mask:
> +   case nir_intrinsic_load_subgroup_lt_mask:
> +      unreachable("not reached");
> +
>     case nir_intrinsic_vote_any: {
>        const fs_builder ubld = bld.exec_all();
>        ubld.MOV(brw_flag_reg(0, 0), brw_imm_uw(0));
> @@ -4126,6 +4137,36 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
>                      bld.SEL(dest, dest, brw_imm_d(0)));
>        break;
>     }
> +
> +   case nir_intrinsic_ballot: {
> +      const fs_reg value = retype(get_nir_src(instr->src[0]),
> +                                  BRW_REGISTER_TYPE_UD);
> +      const struct brw_reg flag = retype(brw_flag_reg(0, 0),
> +                                         BRW_REGISTER_TYPE_UD);
> +
> +      bld.exec_all().MOV(flag, brw_imm_ud(0u));
> +      bld.CMP(bld.null_reg_ud(), value, brw_imm_ud(0u), BRW_CONDITIONAL_NZ);
> +
> +      dest.type = BRW_REGISTER_TYPE_UQ;
> +      bld.MOV(dest, flag);
> +      break;
> +   }
> +
> +   case nir_intrinsic_read_invocation: {
> +      const fs_reg value = get_nir_src(instr->src[0]);
> +      const fs_reg invocation = get_nir_src(instr->src[1]);
> +      bld.MOV(retype(dest, BRW_REGISTER_TYPE_D),
> +              bld.emit_uniformize(value, invocation));
> +      break;
> +   }
> +
> +   case nir_intrinsic_read_first_invocation: {
> +      const fs_reg value = get_nir_src(instr->src[0]);
> +      bld.MOV(retype(dest, BRW_REGISTER_TYPE_D),
> +              bld.emit_uniformize(value));
> +      break;
> +   }
> +
>     default:
>        unreachable("unknown intrinsic");
>     }
> diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c
> index cede77fbc8..ce21c01669 100644
> --- a/src/intel/compiler/brw_nir.c
> +++ b/src/intel/compiler/brw_nir.c
> @@ -620,6 +620,7 @@ brw_preprocess_nir(const struct brw_compiler *compiler, nir_shader *nir)
>  
>     OPT(nir_lower_tex, &tex_options);
>     OPT(nir_normalize_cubemap_coords);
> +   OPT(nir_lower_read_invocation_to_scalar);
>  
>     OPT(nir_lower_global_vars_to_local);
>  
> 

Patches 14-15 are:
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
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