[Mesa-dev] [PATCH 11/22] i965: Prepare tex, img and rt state emission for isl based miptrees
Topi Pohjolainen
topi.pohjolainen at gmail.com
Tue Jul 18 08:46:21 UTC 2017
Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
---
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 21 ++++++++++++++++-----
1 file changed, 16 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 3f2ca82fdb..45ac106f3f 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -80,9 +80,13 @@ get_isl_surf(struct brw_context *brw, struct intel_mipmap_tree *mt,
uint32_t *tile_x, uint32_t *tile_y,
uint32_t *offset, struct isl_surf *surf)
{
- intel_miptree_get_isl_surf(brw, mt, surf);
+ if (mt->surf.size > 0) {
+ *surf = mt->surf;
+ } else {
+ intel_miptree_get_isl_surf(brw, mt, surf);
- surf->dim = get_isl_surf_dim(target);
+ surf->dim = get_isl_surf_dim(target);
+ }
const enum isl_dim_layout dim_layout =
get_isl_dim_layout(&brw->screen->devinfo, mt->surf.tiling, target,
@@ -553,9 +557,16 @@ brw_update_texture_surface(struct gl_context *ctx,
/* If this is a view with restricted NumLayers, then our effective depth
* is not just the miptree depth.
*/
- const unsigned view_num_layers =
- (obj->Immutable && obj->Target != GL_TEXTURE_3D) ? obj->NumLayers :
- mt->logical_depth0;
+ unsigned view_num_layers;
+ if (obj->Immutable && obj->Target != GL_TEXTURE_3D) {
+ view_num_layers = obj->NumLayers;
+ } else if (mt->surf.size > 0) {
+ view_num_layers = mt->surf.dim == ISL_SURF_DIM_3D ?
+ mt->surf.logical_level0_px.depth :
+ mt->surf.logical_level0_px.array_len;
+ } else {
+ view_num_layers = mt->logical_depth0;
+ }
/* Handling GL_ALPHA as a surface format override breaks 1.30+ style
* texturing functions that return a float, as our code generation always
--
2.11.0
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