[Mesa-dev] [PATCH 16/17] squash: i965/gen4: Force x-tiling for color surfaces

[Topi Pohjolainen]

This is what brw_miptree_choose_tiling() currently does even
though blorp is available.

Before enabling y-tiled one needs to fix, for example, batch
wrapping caused by mipmap offsets not being tile aligned
anymore and intel_renderbuffer_move_to_temp() kicking in where it
didn't before as x-tiled met the alignment constraints.

Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 7b2f98cc1b..af5d37bc47 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -953,8 +953,13 @@ miptree_create(struct brw_context *brw,
    if (layout_flags & MIPTREE_LAYOUT_ACCELERATED_UPLOAD)
       alloc_flags |= BO_ALLOC_FOR_RENDER;
 
-   const isl_tiling_flags_t tiling_flags = force_linear_tiling(layout_flags) ?
+   isl_tiling_flags_t tiling_flags = force_linear_tiling(layout_flags) ?
       ISL_TILING_LINEAR_BIT : ISL_TILING_ANY_MASK;
+
+   /* TODO: This used to be because there wasn't BLORP to handle Y-tiling. */
+   if (brw->gen < 6)
+      tiling_flags &= ~ISL_TILING_Y0_BIT;
+
    struct intel_mipmap_tree *mt = make_surface(
                                      brw, target, format,
                                      first_level, last_level,
-- 
2.11.0