[Mesa-dev] [PATCH] intel/isl: Add support for blitter restrictions

[Jason Ekstrand]

---
 src/intel/isl/isl.c      | 42 +++++++++++++++++++++++++++++++++++++++---
 src/intel/isl/isl.h      |  1 +
 src/intel/isl/isl_gen4.c |  5 +++++
 3 files changed, 45 insertions(+), 3 deletions(-)

diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index 7d1356f..26310bf 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -1168,6 +1168,8 @@ isl_calc_row_pitch_alignment(const struct isl_surf_init_info *surf_info,
    if (tile_info->tiling != ISL_TILING_LINEAR)
       return tile_info->phys_extent_B.width;
 
+   uint32_t alignment = 1;
+
    /* From the Broadwel PRM >> Volume 2d: Command Reference: Structures >>
     * RENDER_SURFACE_STATE Surface Pitch (p349):
     *
@@ -1186,14 +1188,26 @@ isl_calc_row_pitch_alignment(const struct isl_surf_init_info *surf_info,
    const uint32_t bs = fmtl->bpb / 8;
 
    if (surf_info->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) {
+      assert(isl_is_pow2(bs));
       if (isl_format_is_yuv(surf_info->format)) {
-         return 2 * bs;
+         alignment = MAX2(alignment, 2 * bs);
       } else  {
-         return bs;
+         alignment = MAX2(alignment, bs);
       }
    }
 
-   return 1;
+   if (surf_info->usage & ISL_SURF_USAGE_BLIT_BIT) {
+      /* From the Broadwell PRM docs for XY_SRC_COPY_BLT::SourceBaseAddress:
+       *
+       *    "Base address of the destination surface: X=0, Y=0. Lower 32bits
+       *    of the 48bit addressing. When Src Tiling is enabled (Bit_15
+       *    enabled), this address must be 4KB-aligned. When Tiling is not
+       *    enabled, this address should be CL (64byte) aligned."
+       */
+      alignment = MAX2(alignment, 64);
+   }
+
+   return alignment;
 }
 
 static uint32_t
@@ -1319,6 +1333,28 @@ isl_calc_row_pitch(const struct isl_device *dev,
    if (surf_info->usage & ISL_SURF_USAGE_STENCIL_BIT)
       isl_finishme("validate row pitch of stencil surfaces");
 
+   if (surf_info->usage & ISL_SURF_USAGE_BLIT_BIT) {
+      /* According to the Ivy Bridge PRM, Vol1 Part4, section 1.2.1.2
+       * (Graphics Data Size Limitations):
+       *
+       *    The BLT engine is capable of transferring very large quantities of
+       *    graphics data. Any graphics data read from and written to the
+       *    destination is permitted to represent a number of pixels that
+       *    occupies up to 65,536 scan lines and up to 32,768 bytes per scan
+       *    line at the destination. The maximum number of pixels that may be
+       *    represented per scan line’s worth of graphics data depends on the
+       *    color depth.
+       *
+       * The blitter's pitch is a signed 16-bit integer, but measured in bytes
+       * for linear surfaces and DWords for tiled surfaces.  So the maximum
+       * pitch is 32k linear and 128k tiled.
+       */
+      const uint32_t blt_pitch =
+         tile_info->tiling == ISL_TILING_LINEAR ? row_pitch : row_pitch / 4;
+      if (blt_pitch > 32768)
+         return false;
+   }
+
  done:
    *out_row_pitch = row_pitch;
    return true;
diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h
index 92d2ffc..359bf88 100644
--- a/src/intel/isl/isl.h
+++ b/src/intel/isl/isl.h
@@ -796,6 +796,7 @@ typedef uint64_t isl_surf_usage_flags_t;
 #define ISL_SURF_USAGE_HIZ_BIT                 (1u << 13)
 #define ISL_SURF_USAGE_MCS_BIT                 (1u << 14)
 #define ISL_SURF_USAGE_CCS_BIT                 (1u << 15)
+#define ISL_SURF_USAGE_BLIT_BIT                (1u << 16)
 /** @} */
 
 /**
diff --git a/src/intel/isl/isl_gen4.c b/src/intel/isl/isl_gen4.c
index 14706c8..1b8dd74 100644
--- a/src/intel/isl/isl_gen4.c
+++ b/src/intel/isl/isl_gen4.c
@@ -75,6 +75,11 @@ isl_gen4_filter_tiling(const struct isl_device *dev,
       *flags &= (ISL_TILING_LINEAR_BIT | ISL_TILING_X_BIT);
    }
 
+   if (info->usage & ISL_SURF_USAGE_BLIT_BIT) {
+      /* The blitter doesn't support Y-tiling until gen6 */
+      *flags &= (ISL_TILING_LINEAR_BIT | ISL_TILING_X_BIT);
+   }
+
    assert(info->samples == 1);
 
    /* From the g35 PRM, Volume 1, 11.5.5, "Per-Stream Tile Format Support":
-- 
2.5.0.400.gff86faf