[Mesa-dev] [PATCH] intel/isl: Add support for blitter restrictions

[Jason Ekstrand]

On Fri, Jul 21, 2017 at 12:27 PM, Chris Wilson <chris at chris-wilson.co.uk>
wrote:

> Quoting Jason Ekstrand (2017-07-21 20:11:27)
> > +   if (surf_info->usage & ISL_SURF_USAGE_BLIT_BIT) {
> > +      /* According to the Ivy Bridge PRM, Vol1 Part4, section 1.2.1.2
> > +       * (Graphics Data Size Limitations):
> > +       *
> > +       *    The BLT engine is capable of transferring very large
> quantities of
> > +       *    graphics data. Any graphics data read from and written to
> the
> > +       *    destination is permitted to represent a number of pixels
> that
> > +       *    occupies up to 65,536 scan lines and up to 32,768 bytes per
> scan
> > +       *    line at the destination. The maximum number of pixels that
> may be
> > +       *    represented per scan line’s worth of graphics data depends
> on the
> > +       *    color depth.
> > +       *
> > +       * The blitter's pitch is a signed 16-bit integer, but measured
> in bytes
> > +       * for linear surfaces and DWords for tiled surfaces.  So the
> maximum
> > +       * pitch is 32k linear and 128k tiled.
> > +       */
> > +      const uint32_t blt_pitch =
> > +         tile_info->tiling == ISL_TILING_LINEAR ? row_pitch : row_pitch
> / 4;
> > +      if (blt_pitch > 32768)
> > +         return false;
>
> Ben will probably remember better since he did the same limits for GL,
> but isn't the field for pitch in XY_SRC_COPY a s16 (as it allows
> negative pitches)? So that test should be >= 32768.


Yes, yes it should.

Also, I did some more reading and it's not a pitch restriction at all.
It's a restriction on base address.  The only reason why we treat it as a
pitch restriction in GL is because that ensures that most miplevels are
aligned to 64 bits (not all!) and got us to not notice the real problem.

--Jason
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