[Mesa-dev] [PATCH 5/5] i965/clear: Don't perform redundant depth clears

[Jason Ekstrand]

I just remembered that we never merged these.  IIRC, it's about 3% on 
Manhattan.


On June 14, 2017 6:54:41 PM Jason Ekstrand <jason at jlekstrand.net> wrote:

> We already have this little optimization for color clears.  Now that
> we're actually tracking whether or not a slice has any fast-clear
> blocks, It's easy enough to add for depth clears too.
> ---
>  src/mesa/drivers/dri/i965/brw_clear.c         | 34 ++++++++++++++++++++++++---
>  src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 14 ++++++++++-
>  2 files changed, 44 insertions(+), 4 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_clear.c 
> b/src/mesa/drivers/dri/i965/brw_clear.c
> index 99ddc4e..5fa4ae7 100644
> --- a/src/mesa/drivers/dri/i965/brw_clear.c
> +++ b/src/mesa/drivers/dri/i965/brw_clear.c
> @@ -200,9 +200,37 @@ brw_fast_clear_depth(struct gl_context *ctx)
>        mt->fast_clear_color.f32[0] = ctx->Depth.Clear;
>     }
>
> -   intel_hiz_exec(brw, mt, depth_irb->mt_level,
> -                  depth_irb->mt_layer, num_layers,
> -                  BLORP_HIZ_OP_DEPTH_CLEAR);
> +   bool need_clear = false;
> +   for (unsigned a = 0; a < num_layers; a++) {
> +      enum isl_aux_state aux_state =
> +         intel_miptree_get_aux_state(mt, depth_irb->mt_level,
> +                                     depth_irb->mt_layer + a);
> +
> +      if (aux_state != ISL_AUX_STATE_CLEAR) {
> +         need_clear = true;
> +         break;
> +      }
> +   }
> +
> +   if (!need_clear) {
> +      /* If all of the layers we intend to clear are already in the clear
> +       * state then simply updating the miptree fast clear value is sufficient
> +       * to change their clear value.
> +       */
> +      return true;
> +   }
> +
> +   for (unsigned a = 0; a < num_layers; a++) {
> +      enum isl_aux_state aux_state =
> +         intel_miptree_get_aux_state(mt, depth_irb->mt_level,
> +                                     depth_irb->mt_layer + a);
> +
> +      if (aux_state != ISL_AUX_STATE_CLEAR) {
> +         intel_hiz_exec(brw, mt, depth_irb->mt_level,
> +                        depth_irb->mt_layer + a, 1,
> +                        BLORP_HIZ_OP_DEPTH_CLEAR);
> +      }
> +   }
>
>     /* Now, the HiZ buffer contains data that needs to be resolved to the depth
>      * buffer.
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> index c19d2d5..8b893dd 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> @@ -2217,8 +2217,20 @@ intel_miptree_prepare_hiz_access(struct brw_context 
> *brw,
>                                   uint32_t level, uint32_t layer,
>                                   bool hiz_supported, bool fast_clear_supported)
>  {
> +   enum isl_aux_state aux_state = intel_miptree_get_aux_state(mt, level, 
> layer);
> +
> +   /* On Sandy Bridge, any usage of depth with HiZ enabled is liable to flush
> +    * out clear color blocks.  If the slice is in the clear state, it should
> +    * now be considered to be in the compressed with clear state.
> +    */
> +   if (brw->gen == 6 && aux_state == ISL_AUX_STATE_CLEAR && hiz_supported) {
> +      assert(fast_clear_supported);
> +      intel_miptree_set_aux_state(brw, mt, level, layer, 1,
> +                                  ISL_AUX_STATE_COMPRESSED_CLEAR);
> +   }
> +
>     enum blorp_hiz_op hiz_op = BLORP_HIZ_OP_NONE;
> -   switch (intel_miptree_get_aux_state(mt, level, layer)) {
> +   switch (aux_state) {
>     case ISL_AUX_STATE_CLEAR:
>     case ISL_AUX_STATE_COMPRESSED_CLEAR:
>        if (!hiz_supported || !fast_clear_supported)
> --
> 2.5.0.400.gff86faf
>