[Mesa-dev] [PATCH 7/7] i965: Drop non-LLC lunacy in the program cache code.

[Emil Velikov]

Hi Ken,

Admittedly I'm not an expert in the area, so perhaps a rather silly question.

On 22 July 2017 at 00:17, Kenneth Graunke <kenneth at whitecape.org> wrote:

> +#ifdef USE_SSE41
> +      if (!cache->bo->cache_coherent && cpu_has_sse4_1)
> +         _mesa_streaming_load_memcpy(map, cache->map, cache->next_offset);
> +      else
> +#endif
> +         memcpy(map, cache->map, cache->next_offset);
The other user of _mesa_streaming_load_memcpy -
intel_miptree_map/intel_miptree_map_movntdqa does not seem to check
for the coherency flag.

Which makes me wonder:
Did you intentionally combine the SSE4.1 check with the
!cache_coherent one, should there be a similar check in the miptree
code or the two cases are orthogonal?

Thanks
Emil