[Mesa-dev] [PATCH] radv/ac: realign SI workaround with radeonsi.

[Bas Nieuwenhuizen]

Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>

On Wed, Jul 26, 2017 at 3:34 AM, Dave Airlie <airlied at gmail.com> wrote:
> From: Dave Airlie <airlied at redhat.com>
>
> This ports: da7453666ae
> radeonsi: don't apply the Z export bug workaround to Hainan
> to radv.
>
> Just noticed in passing.
>
> Fixes: f4e499ec7 (radv: add initial non-conformant radv vulkan driver)
> Signed-off-by: Dave Airlie <airlied at redhat.com>
> ---
>  src/amd/common/ac_nir_to_llvm.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
> index 9a69066..a427f48 100644
> --- a/src/amd/common/ac_nir_to_llvm.c
> +++ b/src/amd/common/ac_nir_to_llvm.c
> @@ -5815,10 +5815,11 @@ si_export_mrt_z(struct nir_to_llvm_context *ctx,
>                 args.enabled_channels |= 0x4;
>         }
>
> -       /* SI (except OLAND) has a bug that it only looks
> +       /* SI (except OLAND and HAINAN) has a bug that it only looks
>          * at the X writemask component. */
>         if (ctx->options->chip_class == SI &&
> -           ctx->options->family != CHIP_OLAND)
> +           ctx->options->family != CHIP_OLAND &&
> +           ctx->options->family != CHIP_HAINAN)
>                 args.enabled_channels |= 0x1;
>
>         ac_build_export(&ctx->ac, &args);
> --
> 2.9.4
>
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