[Mesa-dev] [PATCH 6/6] i965/miptree: Use isl_image_offset
Topi Pohjolainen
topi.pohjolainen at gmail.com
Wed Jul 26 19:28:38 UTC 2017
Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
---
src/mesa/drivers/dri/i965/brw_blorp.c | 2 +-
src/mesa/drivers/dri/i965/brw_context.c | 1 -
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 13 +++----
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 49 +++++++++++-------------
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 19 +--------
src/mesa/drivers/dri/i965/intel_pixel_draw.c | 3 +-
src/mesa/drivers/dri/i965/intel_pixel_read.c | 2 +-
src/mesa/drivers/dri/i965/intel_tex.c | 3 +-
src/mesa/drivers/dri/i965/intel_tex_image.c | 2 +-
9 files changed, 36 insertions(+), 58 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c
index b2987ca4fa..ebe4a051f4 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -149,7 +149,7 @@ blorp_surf_for_miptree(struct brw_context *brw,
surf->surf = &mt->surf;
surf->addr = (struct blorp_address) {
.buffer = mt->bo,
- .offset = mt->offset,
+ .offset = mt->offset.tile_aligned_byte_offset,
.read_domains = is_render_target ? I915_GEM_DOMAIN_RENDER :
I915_GEM_DOMAIN_SAMPLER,
.write_domain = is_render_target ? I915_GEM_DOMAIN_RENDER : 0,
diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index d0b22d4342..ddd50a16fc 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -1513,7 +1513,6 @@ intel_process_dri2_buffer(struct brw_context *brw,
intel_miptree_create_for_bo(brw,
bo,
intel_rb_format(rb),
- 0,
drawable->w,
drawable->h,
1,
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 2da0984c0f..86e903888c 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -135,12 +135,7 @@ brw_emit_surface_state(struct brw_context *brw,
uint32_t mocs, uint32_t *surf_offset, int surf_index,
unsigned read_domains, unsigned write_domains)
{
- struct isl_image_offset offset = {
- .tile_aligned_byte_offset = mt->offset,
- .intra_tile_x = mt->level[0].level_x,
- .intra_tile_y = mt->level[0].level_y
- };
-
+ struct isl_image_offset offset = mt->offset;
struct isl_surf surf;
get_isl_surf(brw, mt, target, &view, &offset, &surf);
@@ -1648,8 +1643,10 @@ update_image_surface(struct brw_context *brw,
if (format == ISL_FORMAT_RAW) {
brw_emit_buffer_surface_state(
- brw, surf_offset, mt->bo, mt->offset,
- format, mt->bo->size - mt->offset, 1 /* pitch */,
+ brw, surf_offset, mt->bo, mt->offset.tile_aligned_byte_offset,
+ format,
+ mt->bo->size - mt->offset.tile_aligned_byte_offset,
+ 1 /* pitch */,
access != GL_READ_ONLY);
} else {
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index cab888f04d..d0546851b4 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -757,8 +757,6 @@ intel_miptree_create(struct brw_context *brw,
if (!mt)
return NULL;
- mt->offset = 0;
-
if (!intel_miptree_alloc_aux(brw, mt)) {
intel_miptree_release(&mt);
return NULL;
@@ -771,7 +769,6 @@ struct intel_mipmap_tree *
intel_miptree_create_for_bo(struct brw_context *brw,
struct brw_bo *bo,
mesa_format format,
- uint32_t offset,
uint32_t width,
uint32_t height,
uint32_t depth,
@@ -817,12 +814,6 @@ intel_miptree_create_for_bo(struct brw_context *brw,
brw_bo_get_tiling(bo, &tiling, &swizzle);
- /* Nothing will be able to use this miptree with the BO if the offset isn't
- * aligned.
- */
- if (tiling != I915_TILING_NONE)
- assert(offset % 4096 == 0);
-
/* miptrees can't handle negative pitch. If you need flipping of images,
* that's outside of the scope of the mt.
*/
@@ -845,7 +836,6 @@ intel_miptree_create_for_bo(struct brw_context *brw,
brw_bo_reference(bo);
mt->bo = bo;
- mt->offset = offset;
if (!(layout_flags & MIPTREE_LAYOUT_DISABLE_AUX))
intel_miptree_choose_aux_usage(brw, mt);
@@ -874,13 +864,13 @@ miptree_create_for_planar_image(struct brw_context *brw,
*/
struct intel_mipmap_tree *mt =
intel_miptree_create_for_bo(brw, image->bo, format,
- image->offsets[index],
width, height, 1,
image->strides[index],
MIPTREE_LAYOUT_DISABLE_AUX);
if (mt == NULL)
return NULL;
+ mt->offset.tile_aligned_byte_offset = image->offsets[index];
mt->target = target;
if (i == 0)
@@ -955,14 +945,22 @@ intel_miptree_create_for_dri_image(struct brw_context *brw,
*/
struct intel_mipmap_tree *mt =
intel_miptree_create_for_bo(brw, image->bo, format,
- image->offset, image->width, image->height, 1,
+ image->width, image->height, 1,
image->pitch, mt_layout_flags);
if (mt == NULL)
return NULL;
mt->target = target;
- mt->level[0].level_x = image->tile_x;
- mt->level[0].level_y = image->tile_y;
+
+ mt->offset.tile_aligned_byte_offset = image->offset;
+ mt->offset.intra_tile_x = image->tile_x;
+ mt->offset.intra_tile_y = image->tile_y;
+
+ /* Nothing will be able to use this miptree with the BO if the offset isn't
+ * aligned.
+ */
+ if (mt->surf.tiling != ISL_TILING_LINEAR)
+ assert(mt->offset.tile_aligned_byte_offset % 4096 == 0);
/* From "OES_EGL_image" error reporting. We report GL_INVALID_OPERATION
* for EGL images from non-tile aligned sufaces in gen4 hw and earlier which has
@@ -1224,8 +1222,8 @@ intel_miptree_get_image_offset(const struct intel_mipmap_tree *mt,
GLuint *x, GLuint *y)
{
if (level == 0 && slice == 0) {
- *x = mt->level[0].level_x;
- *y = mt->level[0].level_y;
+ *x = mt->offset.intra_tile_x;
+ *y = mt->offset.intra_tile_y;
return;
}
@@ -1235,8 +1233,9 @@ intel_miptree_get_image_offset(const struct intel_mipmap_tree *mt,
* slice in an imported buffer object.
* See intel_miptree_create_for_dri_image().
*/
- assert(mt->level[0].level_x == 0);
- assert(mt->level[0].level_y == 0);
+ assert(mt->offset.intra_tile_x == 0);
+ assert(mt->offset.intra_tile_y == 0);
+ assert(mt->offset.tile_aligned_byte_offset == 0);
/* Given level is relative to level zero while the miptree may be
* represent just a subset of all levels starting from 'first_level'.
@@ -1319,18 +1318,16 @@ intel_miptree_get_tile_offsets(const struct intel_mipmap_tree *mt,
* consists of tile aligned byte offset and intra tile x,y coordinates.
*/
if (level == 0 && slice == 0) {
- image_offset->intra_tile_x = mt->level[0].level_x;
- image_offset->intra_tile_y = mt->level[0].level_y;
- image_offset->tile_aligned_byte_offset = mt->offset;
+ *image_offset = mt->offset;
return;
}
/* Only single slices can be imported - mipmapped and arrayed always
* start from the beginning of the underlying buffer object.
*/
- assert(mt->offset == 0);
- assert(mt->level[0].level_x == 0);
- assert(mt->level[0].level_y == 0);
+ assert(mt->offset.intra_tile_x == 0);
+ assert(mt->offset.intra_tile_y == 0);
+ assert(mt->offset.tile_aligned_byte_offset == 0);
uint32_t x, y;
intel_miptree_get_image_offset(mt, level, slice, &x, &y);
@@ -2900,7 +2897,7 @@ intel_miptree_map_gtt(struct brw_context *brw,
if (base == NULL)
map->ptr = NULL;
else {
- base += mt->offset;
+ base += mt->offset.tile_aligned_byte_offset;
/* Note that in the case of cube maps, the caller must have passed the
* slice number referencing the face.
@@ -3026,7 +3023,7 @@ intel_miptree_map_movntdqa(struct brw_context *brw,
if (!src)
return;
- src += mt->offset;
+ src += mt->offset.tile_aligned_byte_offset;
src += image_y * mt->surf.row_pitch;
src += image_x * mt->cpp;
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index d9d2ce9ee2..d9ccf95206 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -94,11 +94,6 @@ struct intel_miptree_map {
*/
struct intel_mipmap_level
{
- /** Offset to this miptree level, used in computing x_offset. */
- GLuint level_x;
- /** Offset to this miptree level, used in computing y_offset. */
- GLuint level_y;
-
/**
* \brief Is HiZ enabled for this level?
*
@@ -184,6 +179,7 @@ struct intel_miptree_aux_buffer
struct intel_mipmap_tree
{
struct isl_surf surf;
+ struct isl_image_offset offset;
/**
* Buffer object containing the surface.
@@ -244,18 +240,6 @@ struct intel_mipmap_tree
struct intel_mipmap_level level[MAX_TEXTURE_LEVELS];
/**
- * Offset into bo where the surface starts.
- *
- * @see intel_mipmap_tree::bo
- *
- * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
- * @see 3DSTATE_DEPTH_BUFFER.SurfaceBaseAddress
- * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceBaseAddress
- * @see 3DSTATE_STENCIL_BUFFER.SurfaceBaseAddress
- */
- uint32_t offset;
-
- /**
* \brief HiZ aux buffer
*
* To allocate the hiz buffer, use intel_miptree_alloc_hiz().
@@ -378,7 +362,6 @@ struct intel_mipmap_tree *
intel_miptree_create_for_bo(struct brw_context *brw,
struct brw_bo *bo,
mesa_format format,
- uint32_t offset,
uint32_t width,
uint32_t height,
uint32_t depth,
diff --git a/src/mesa/drivers/dri/i965/intel_pixel_draw.c b/src/mesa/drivers/dri/i965/intel_pixel_draw.c
index 519e059672..ab9b8c1a23 100644
--- a/src/mesa/drivers/dri/i965/intel_pixel_draw.c
+++ b/src/mesa/drivers/dri/i965/intel_pixel_draw.c
@@ -115,13 +115,14 @@ do_blit_drawpixels(struct gl_context * ctx,
intel_miptree_create_for_bo(brw,
src_buffer,
irb->mt->format,
- src_offset,
width, height, 1,
src_stride,
0);
if (!pbo_mt)
return false;
+ pbo_mt->offset.tile_aligned_byte_offset = src_offset;
+
if (!intel_miptree_blit(brw,
pbo_mt, 0, 0,
0, 0, src_flip,
diff --git a/src/mesa/drivers/dri/i965/intel_pixel_read.c b/src/mesa/drivers/dri/i965/intel_pixel_read.c
index cd4fbab097..f170a1eab5 100644
--- a/src/mesa/drivers/dri/i965/intel_pixel_read.c
+++ b/src/mesa/drivers/dri/i965/intel_pixel_read.c
@@ -200,7 +200,7 @@ intel_readpixels_tiled_memcpy(struct gl_context * ctx,
xoffset * cpp, (xoffset + width) * cpp,
yoffset, yoffset + height,
pixels - (ptrdiff_t) yoffset * dst_pitch - (ptrdiff_t) xoffset * cpp,
- map + irb->mt->offset,
+ map + irb->mt->offset.tile_aligned_byte_offset,
dst_pitch, irb->mt->surf.row_pitch,
brw->has_swizzling,
irb->mt->surf.tiling,
diff --git a/src/mesa/drivers/dri/i965/intel_tex.c b/src/mesa/drivers/dri/i965/intel_tex.c
index 7ce2ceb9a2..57d4d9cf7f 100644
--- a/src/mesa/drivers/dri/i965/intel_tex.c
+++ b/src/mesa/drivers/dri/i965/intel_tex.c
@@ -342,13 +342,14 @@ intel_set_texture_storage_for_buffer_object(struct gl_context *ctx,
intel_texobj->mt =
intel_miptree_create_for_bo(brw, bo,
image->TexFormat,
- buffer_offset,
image->Width, image->Height, image->Depth,
row_stride,
0);
if (!intel_texobj->mt)
return false;
+ intel_texobj->mt->offset.tile_aligned_byte_offset = buffer_offset;
+
if (!_swrast_init_texture_image(image))
return false;
diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c b/src/mesa/drivers/dri/i965/intel_tex_image.c
index beed1609bd..1fc1ace0fb 100644
--- a/src/mesa/drivers/dri/i965/intel_tex_image.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_image.c
@@ -258,7 +258,7 @@ intelSetTexBuffer2(__DRIcontext *pDRICtx, GLint target,
}
intel_miptree_make_shareable(brw, rb->mt);
- mt = intel_miptree_create_for_bo(brw, rb->mt->bo, texFormat, 0,
+ mt = intel_miptree_create_for_bo(brw, rb->mt->bo, texFormat,
rb->Base.Base.Width,
rb->Base.Base.Height,
1, rb->mt->surf.row_pitch, 0);
--
2.11.0
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