[Mesa-dev] [PATCH 3/3] radeonsi: rely on CLEAR_STATE for clearing UCP and blend color registers

[Marek Olšák]

From: Marek Olšák <marek.olsak at amd.com>

---
 src/gallium/drivers/radeonsi/si_hw_context.c | 8 ++++++--
 src/gallium/drivers/radeonsi/si_pipe.h       | 2 ++
 src/gallium/drivers/radeonsi/si_state.c      | 4 ++++
 3 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_hw_context.c b/src/gallium/drivers/radeonsi/si_hw_context.c
index cceb827..92d0cc5 100644
--- a/src/gallium/drivers/radeonsi/si_hw_context.c
+++ b/src/gallium/drivers/radeonsi/si_hw_context.c
@@ -220,29 +220,33 @@ void si_begin_new_cs(struct si_context *ctx)
 	/* CLEAR_STATE disables all colorbuffers, so only enable bound ones. */
 	ctx->framebuffer.dirty_cbufs =
 		u_bit_consecutive(0, ctx->framebuffer.state.nr_cbufs);
 	/* CLEAR_STATE disables the zbuffer, so only enable it if it's bound. */
 	ctx->framebuffer.dirty_zsbuf = ctx->framebuffer.state.zsbuf != NULL;
 	/* This should always be marked as dirty to set the framebuffer scissor
 	 * at least. */
 	si_mark_atom_dirty(ctx, &ctx->framebuffer.atom);
 
 	si_mark_atom_dirty(ctx, &ctx->clip_regs);
-	si_mark_atom_dirty(ctx, &ctx->clip_state.atom);
+	/* CLEAR_STATE sets zeros. */
+	if (ctx->clip_state.any_nonzeros)
+		si_mark_atom_dirty(ctx, &ctx->clip_state.atom);
 	ctx->msaa_sample_locs.nr_samples = 0;
 	si_mark_atom_dirty(ctx, &ctx->msaa_sample_locs.atom);
 	si_mark_atom_dirty(ctx, &ctx->msaa_config);
 	/* CLEAR_STATE sets 0xffff. */
 	if (ctx->sample_mask.sample_mask != 0xffff)
 		si_mark_atom_dirty(ctx, &ctx->sample_mask.atom);
 	si_mark_atom_dirty(ctx, &ctx->cb_render_state);
-	si_mark_atom_dirty(ctx, &ctx->blend_color.atom);
+	/* CLEAR_STATE sets zeros. */
+	if (ctx->blend_color.any_nonzeros)
+		si_mark_atom_dirty(ctx, &ctx->blend_color.atom);
 	si_mark_atom_dirty(ctx, &ctx->db_render_state);
 	si_mark_atom_dirty(ctx, &ctx->stencil_ref.atom);
 	si_mark_atom_dirty(ctx, &ctx->spi_map);
 	si_mark_atom_dirty(ctx, &ctx->b.streamout.enable_atom);
 	si_mark_atom_dirty(ctx, &ctx->b.render_cond_atom);
 	si_all_descriptors_begin_new_cs(ctx);
 	si_all_resident_buffers_begin_new_cs(ctx);
 
 	ctx->b.scissors.dirty_mask = (1 << R600_MAX_VIEWPORTS) - 1;
 	ctx->b.viewports.dirty_mask = (1 << R600_MAX_VIEWPORTS) - 1;
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index 2e8a3bf..f7e0486 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -120,20 +120,21 @@ struct si_screen {
 
 	struct util_queue		shader_compiler_queue_low_priority;
 	/* Use at most 2 low priority threads on quadcore and better.
 	 * We want to minimize the impact on multithreaded Mesa. */
 	LLVMTargetMachineRef		tm_low_priority[2]; /* at most 2 threads */
 };
 
 struct si_blend_color {
 	struct r600_atom		atom;
 	struct pipe_blend_color		state;
+	bool				any_nonzeros;
 };
 
 struct si_sampler_view {
 	struct pipe_sampler_view	base;
         /* [0..7] = image descriptor
          * [4..7] = buffer descriptor */
 	uint32_t			state[8];
 	uint32_t			fmask_state[8];
 	const struct legacy_surf_level	*base_level_info;
 	ubyte				base_level;
@@ -185,20 +186,21 @@ struct si_framebuffer {
 	ubyte				color_is_int8;
 	ubyte				color_is_int10;
 	ubyte				dirty_cbufs;
 	bool				dirty_zsbuf;
 	bool				any_dst_linear;
 };
 
 struct si_clip_state {
 	struct r600_atom		atom;
 	struct pipe_clip_state		state;
+	bool				any_nonzeros;
 };
 
 struct si_sample_locs {
 	struct r600_atom	atom;
 	unsigned		nr_samples;
 };
 
 struct si_sample_mask {
 	struct r600_atom	atom;
 	uint16_t		sample_mask;
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index ac76b12..7dadc4a 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -624,47 +624,51 @@ static void si_bind_blend_state(struct pipe_context *ctx, void *state)
 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
 {
 	struct si_context *sctx = (struct si_context *)ctx;
 	si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
 }
 
 static void si_set_blend_color(struct pipe_context *ctx,
 			       const struct pipe_blend_color *state)
 {
 	struct si_context *sctx = (struct si_context *)ctx;
+	static const struct pipe_blend_color zeros;
 
 	sctx->blend_color.state = *state;
+	sctx->blend_color.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
 	si_mark_atom_dirty(sctx, &sctx->blend_color.atom);
 }
 
 static void si_emit_blend_color(struct si_context *sctx, struct r600_atom *atom)
 {
 	struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
 
 	radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
 	radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
 }
 
 /*
  * Clipping
  */
 
 static void si_set_clip_state(struct pipe_context *ctx,
 			      const struct pipe_clip_state *state)
 {
 	struct si_context *sctx = (struct si_context *)ctx;
 	struct pipe_constant_buffer cb;
+	static const struct pipe_clip_state zeros;
 
 	if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
 		return;
 
 	sctx->clip_state.state = *state;
+	sctx->clip_state.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
 	si_mark_atom_dirty(sctx, &sctx->clip_state.atom);
 
 	cb.buffer = NULL;
 	cb.user_buffer = state->ucp;
 	cb.buffer_offset = 0;
 	cb.buffer_size = 4*4*8;
 	si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb);
 	pipe_resource_reference(&cb.buffer, NULL);
 }
 
-- 
2.7.4