[Mesa-dev] [PATCH 12/14] radeonsi: if FMASK is disabled, set CB_COLORi_FMASK = CB_COLORi_BASE properly

[Marek Olšák]

From: Marek Olšák <marek.olsak at amd.com>

---
 src/gallium/drivers/radeonsi/si_state.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index c151a98..6e67824 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -2755,21 +2755,21 @@ static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom
 		}
 
 		if (tex->dcc_separate_buffer)
 			radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
 						  tex->dcc_separate_buffer,
 						  RADEON_USAGE_READWRITE,
 						  RADEON_PRIO_DCC);
 
 		/* Compute mutable surface parameters. */
 		cb_color_base = tex->resource.gpu_address >> 8;
-		cb_color_fmask = cb_color_base;
+		cb_color_fmask = 0;
 		cb_dcc_base = 0;
 		cb_color_info = cb->cb_color_info | tex->cb_color_info;
 		cb_color_attrib = cb->cb_color_attrib;
 
 		if (tex->fmask.size)
 			cb_color_fmask = (tex->resource.gpu_address + tex->fmask.offset) >> 8;
 
 		/* Set up DCC. */
 		if (vi_dcc_enabled(tex, cb->base.u.tex.level)) {
 			bool is_msaa_resolve_dst = state->cbufs[0] &&
@@ -2787,20 +2787,22 @@ static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom
 		if (sctx->b.chip_class >= GFX9) {
 			struct gfx9_surf_meta_flags meta;
 
 			if (tex->dcc_offset)
 				meta = tex->surface.u.gfx9.dcc;
 			else
 				meta = tex->surface.u.gfx9.cmask;
 
 			/* Set mutable surface parameters. */
 			cb_color_base += tex->surface.u.gfx9.surf_offset >> 8;
+			if (!tex->fmask.size)
+				cb_color_fmask = cb_color_base;
 			cb_color_attrib |= S_028C74_COLOR_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
 					   S_028C74_FMASK_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) |
 					   S_028C74_RB_ALIGNED(meta.rb_aligned) |
 					   S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
 
 			radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 15);
 			radeon_emit(cs, cb_color_base);		/* CB_COLOR0_BASE */
 			radeon_emit(cs, cb_color_base >> 32);	/* CB_COLOR0_BASE_EXT */
 			radeon_emit(cs, cb->cb_color_attrib2);	/* CB_COLOR0_ATTRIB2 */
 			radeon_emit(cs, cb->cb_color_view);	/* CB_COLOR0_VIEW */
@@ -2819,20 +2821,22 @@ static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom
 			radeon_set_context_reg(cs, R_0287A0_CB_MRT0_EPITCH + i * 4,
 					       S_0287A0_EPITCH(tex->surface.u.gfx9.surf.epitch));
 		} else {
 			/* Compute mutable surface parameters (SI-CI-VI). */
 			const struct legacy_surf_level *level_info =
 				&tex->surface.u.legacy.level[cb->base.u.tex.level];
 			unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
 			unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice;
 
 			cb_color_base += level_info->offset >> 8;
+			if (!tex->fmask.size)
+				cb_color_fmask = cb_color_base;
 			if (cb_dcc_base)
 				cb_dcc_base += level_info->dcc_offset >> 8;
 
 			pitch_tile_max = level_info->nblk_x / 8 - 1;
 			slice_tile_max = level_info->nblk_x *
 					 level_info->nblk_y / 64 - 1;
 			tile_mode_index = si_tile_mode_index(tex, cb->base.u.tex.level, false);
 
 			cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
 			cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
-- 
2.7.4