[Mesa-dev] [PATCH 17/24] i965/cnl: Implement new pipe control workaround

[Anuj Phogat]

On Fri, Jun 2, 2017 at 5:08 PM, Jason Ekstrand <jason at jlekstrand.net> wrote:
> On Fri, May 12, 2017 at 4:38 PM, Anuj Phogat <anuj.phogat at gmail.com> wrote:
>>
>> From: Ben Widawsky <benjamin.widawsky at intel.com>
>>
>> GEN10 requires flushing all previous pipe controls before issuing a render
>> target cache flush. The docs seem to fairly explicitly say this is gen10
>> only.
>>
>> V2 (by Anuj): Use flags & PIPE_CONTROL_RENDER_TARGET_FLUSH check. (Ilia)
>>               Use recursive call to brw_emit_pipe_control_flush().
>>
>> Signed-off-by: Ben Widawsky <benjamin.widawsky at intel.com>
>> Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
>> ---
>>  src/mesa/drivers/dri/i965/brw_pipe_control.c | 11 +++++++++++
>>  1 file changed, 11 insertions(+)
>>
>> diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c
>> b/src/mesa/drivers/dri/i965/brw_pipe_control.c
>> index f4ede2d..ecf2fac 100644
>> --- a/src/mesa/drivers/dri/i965/brw_pipe_control.c
>> +++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c
>> @@ -128,6 +128,17 @@ brw_emit_pipe_control_flush(struct brw_context *brw,
>> uint32_t flags)
>>           brw_emit_pipe_control_flush(brw, 0);
>>        }
>>
>> +      if (brw->gen == 10 && (flags & PIPE_CONTROL_RENDER_TARGET_FLUSH)) {
>> +        /* Hardware workaround: CNL
>> +         *
>> +         * "Before sending a PIPE_CONTROL command with bit 12 set, SW
>> +         * must issue another PIPE_CONTROL with Render Target Cache
>> +         * Flush Enable (bit 12) = 0 and Pipe Control Flush Enable
>> +         * (bit 7) = 1."
>
>
> A more specific spec citation would be good.  Maybe something like:
>
> From the "Gen10 Workarounds" page:
>
> In any case, the workaround looks correct although the docs say it only
> applies to A0 stepping.  Is this still even needed?
>
You're right. Now the spec shows it applies only to A0 stepping. Dropping
this patch.
>>
>> +         */
>> +         brw_emit_pipe_control_flush(brw, PIPE_CONTROL_FLUSH_ENABLE);
>> +      }
>> +
>>        BEGIN_BATCH(6);
>>        OUT_BATCH(_3DSTATE_PIPE_CONTROL | (6 - 2));
>>        OUT_BATCH(flags);
>> --
>> 2.9.3
>>
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>
>