[Mesa-dev] [PATCH 03/10] i965: Perform HiZ flush/stall prior to HiZ resolves

[Jason Ekstrand]

Patches 1-3 should have been CC'd to stable.

On Mon, Jun 5, 2017 at 5:55 PM, Jason Ekstrand <jason at jlekstrand.net> wrote:

> ---
>  src/mesa/drivers/dri/i965/brw_blorp.c | 39 +++++++++++++++++++++++-------
> -----
>  1 file changed, 26 insertions(+), 13 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c
> b/src/mesa/drivers/dri/i965/brw_blorp.c
> index 1e4c0de..097903e 100644
> --- a/src/mesa/drivers/dri/i965/brw_blorp.c
> +++ b/src/mesa/drivers/dri/i965/brw_blorp.c
> @@ -1030,7 +1030,12 @@ intel_hiz_exec(struct brw_context *brw, struct
> intel_mipmap_tree *mt,
>     DBG("%s %s to mt %p level %d layers %d-%d\n",
>         __func__, opname, mt, level, start_layer, start_layer + num_layers
> - 1);
>
> -   if (op == BLORP_HIZ_OP_DEPTH_CLEAR) {
> +   /* The following stalls and flushes are only documented to be required
> for
> +    * HiZ clear operations.  However, they also seem to be required for
> the
> +    * HiZ resolve operation which is basically the same as a fast clear
> only a
> +    * different value is written into the HiZ surface.
> +    */
> +   if (op == BLORP_HIZ_OP_DEPTH_CLEAR || op == BLORP_HIZ_OP_HIZ_RESOLVE) {
>        if (brw->gen == 6) {
>           /* From the Sandy Bridge PRM, volume 2 part 1, page 313:
>            *
> @@ -1081,18 +1086,26 @@ intel_hiz_exec(struct brw_context *brw, struct
> intel_mipmap_tree *mt,
>           gen6_blorp_hiz_exec(brw, mt, level, start_layer + a, op);
>     }
>
> -   if (brw->gen == 6 && op == BLORP_HIZ_OP_DEPTH_CLEAR) {
> -      /* From the Sandy Bridge PRM, volume 2 part 1, page 314:
> -       *
> -       *     "DevSNB, DevSNB-B{W/A}]: Depth buffer clear pass must be
> followed
> -       *      by a PIPE_CONTROL command with DEPTH_STALL bit set and Then
> -       *      followed by Depth FLUSH'
> -      */
> -      brw_emit_pipe_control_flush(brw,
> -                                  PIPE_CONTROL_DEPTH_STALL);
>
> -      brw_emit_pipe_control_flush(brw,
> -                                  PIPE_CONTROL_DEPTH_CACHE_FLUSH |
> -                                  PIPE_CONTROL_CS_STALL);
> +   /* The following stalls and flushes are only documented to be required
> for
> +    * HiZ clear operations.  However, they also seem to be required for
> the
> +    * HiZ resolve operation which is basically the same as a fast clear
> only a
> +    * different value is written into the HiZ surface.
> +    */
> +   if (op == BLORP_HIZ_OP_DEPTH_CLEAR || op == BLORP_HIZ_OP_HIZ_RESOLVE) {
> +      if (brw->gen == 6) {
> +         /* From the Sandy Bridge PRM, volume 2 part 1, page 314:
> +          *
> +          *     "DevSNB, DevSNB-B{W/A}]: Depth buffer clear pass must be
> +          *     followed by a PIPE_CONTROL command with DEPTH_STALL bit
> set
> +          *     and Then followed by Depth FLUSH'
> +         */
> +         brw_emit_pipe_control_flush(brw,
> +                                     PIPE_CONTROL_DEPTH_STALL);
> +
> +         brw_emit_pipe_control_flush(brw,
> +                                     PIPE_CONTROL_DEPTH_CACHE_FLUSH |
> +                                     PIPE_CONTROL_CS_STALL);
> +      }
>     }
>  }
> --
> 2.5.0.400.gff86faf
>
>
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