[Mesa-dev] [PATCH] radv: move chip_class extraction down further.

[Dave Airlie]

From: Dave Airlie <airlied at redhat.com>

This seems to matter here in a profile, without this we spend a lot
more time exiting this function with no flush bits.

Signed-off-by: Dave Airlie <airlied at redhat.com>
---
 src/amd/vulkan/si_cmd_buffer.c | 15 ++++++++++-----
 1 file changed, 10 insertions(+), 5 deletions(-)

diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
index a251a1a..47bf553 100644
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_cmd_buffer.c
@@ -690,16 +690,20 @@ si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
 	bool ia_switch_on_eoi = false;
 	bool partial_vs_wave = false;
 	bool partial_es_wave = false;
-	uint32_t num_prims = radv_prims_for_vertices(&cmd_buffer->state.pipeline->graphics.prim_vertex_count, draw_vertex_count);
+	uint32_t num_prims = 0;
 	bool multi_instances_smaller_than_primgroup;
-
+	bool instance_less_than_primgroup_size = false;
 	if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
 		primgroup_size = cmd_buffer->state.pipeline->graphics.tess.num_patches;
 	else if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
 		primgroup_size = 64;  /* recommended with a GS */
 
-	multi_instances_smaller_than_primgroup = indirect_draw || (instanced_draw &&
-								   num_prims < primgroup_size);
+	if (instanced_draw || radv_pipeline_has_gs(cmd_buffer->state.pipeline)) {
+		num_prims = radv_prims_for_vertices(&cmd_buffer->state.pipeline->graphics.prim_vertex_count, draw_vertex_count);
+		instance_less_than_primgroup_size = num_prims < primgroup_size;
+	}
+
+	multi_instances_smaller_than_primgroup = indirect_draw || instance_less_than_primgroup_size;
 	if (radv_pipeline_has_tess(cmd_buffer->state.pipeline)) {
 		/* SWITCH_ON_EOI must be set if PrimID is used. */
 		if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.uses_prim_id ||
@@ -1079,7 +1083,7 @@ void
 si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer)
 {
 	bool is_compute = cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE;
-	enum chip_class chip_class = cmd_buffer->device->physical_device->rad_info.chip_class;
+
 	if (is_compute)
 		cmd_buffer->state.flush_bits &= ~(RADV_CMD_FLAG_FLUSH_AND_INV_CB |
 	                                          RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
@@ -1092,6 +1096,7 @@ si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer)
 	if (!cmd_buffer->state.flush_bits)
 		return;
 
+	enum chip_class chip_class = cmd_buffer->device->physical_device->rad_info.chip_class;
 	radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 128);
 
 	uint32_t *ptr = NULL;
-- 
2.9.4