[Mesa-dev] [PATCH] intel: Fix broxton 2x6 way size computation

[Kenneth Graunke]

On Tuesday, June 6, 2017 4:34:36 PM PDT Anuj Phogat wrote:
> This patch is undoing the changes to way size computation
> in broxton 2x6, made by below commit:
> 
> Commit: 0d576fbfbe912cf3fb9ab594bb31eb58bccf2138
> Author:     Anuj Phogat <anuj.phogat at gmail.com>
> i965: Simplify l3 way size computations
> 
> By making use of l3_banks field in gen_device_info struct
> l3_way_size for gen7+ = 2 * l3_banks.
> 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101306
> Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
> Cc: Jason Ekstrand <jason at jlekstrand.net>
> Cc: Mark Janes <mark.a.janes at intel.com >
> Cc: Francisco Jerez <currojerez at riseup.net>
> ---
> Note: Above bugzilla exposed a bug in our l3 allocation for
> broxton 2x6. We need more changes to fix l3 config. I'll send
> them later to the list. For now this patch brings things back
> to where they were for bxt and unblocks the CI system to be
> utilized for the performance work going on at present.
> ---
>  src/intel/common/gen_l3_config.c | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/src/intel/common/gen_l3_config.c b/src/intel/common/gen_l3_config.c
> index e0825e9..2520838 100644
> --- a/src/intel/common/gen_l3_config.c
> +++ b/src/intel/common/gen_l3_config.c
> @@ -255,6 +255,10 @@ static unsigned
>  get_l3_way_size(const struct gen_device_info *devinfo)
>  {
>     assert(devinfo->l3_banks);
> +
> +   if (devinfo->is_broxton)
> +      return 4;
> +
>     return 2 * devinfo->l3_banks;
>  }
>  
> 

Yeah...it's strange, the docs indicate that there's only 1 bank of L3
on Broxton 2x6, but it seems to have been working with 2...

Acked-by: Kenneth Graunke <kenneth at whitecape.org>

Your patches also changed the number of L3 banks in Kabylake GT 1.5.
It now has more of them, matching GT2 instead of GT1.  I think that's
correct by the documentation.
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