[Mesa-dev] [PATCH 1/3] radv: rename and make global some functions.
Bas Nieuwenhuizen
bas at basnieuwenhuizen.nl
Wed Jun 7 00:03:35 UTC 2017
This series is
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
On Wed, Jun 7, 2017 at 1:18 AM, Dave Airlie <airlied at gmail.com> wrote:
> From: Dave Airlie <airlied at redhat.com>
>
> I want to use these in the pipeline setup stage.
>
> Signed-off-by: Dave Airlie <airlied at redhat.com>
> ---
> src/amd/vulkan/radv_cmd_buffer.c | 24 ++++++++++++------------
> src/amd/vulkan/radv_private.h | 5 +++++
> 2 files changed, 17 insertions(+), 12 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
> index f3187e8..851b2ca 100644
> --- a/src/amd/vulkan/radv_cmd_buffer.c
> +++ b/src/amd/vulkan/radv_cmd_buffer.c
> @@ -394,8 +394,8 @@ static unsigned radv_pack_float_12p4(float x)
> x >= 4096 ? 0xffff : x * 16;
> }
>
> -static uint32_t
> -shader_stage_to_user_data_0(gl_shader_stage stage, bool has_gs, bool has_tess)
> +uint32_t
> +radv_shader_stage_to_user_data_0(gl_shader_stage stage, bool has_gs, bool has_tess)
> {
> switch (stage) {
> case MESA_SHADER_FRAGMENT:
> @@ -421,7 +421,7 @@ shader_stage_to_user_data_0(gl_shader_stage stage, bool has_gs, bool has_tess)
> }
> }
>
> -static struct ac_userdata_info *
> +struct ac_userdata_info *
> radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
> gl_shader_stage stage,
> int idx)
> @@ -436,7 +436,7 @@ radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
> int idx, uint64_t va)
> {
> struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
> - uint32_t base_reg = shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
> + uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
> if (loc->sgpr_idx == -1)
> return;
> assert(loc->num_sgprs == 2);
> @@ -478,7 +478,7 @@ radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
> if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions) {
> uint32_t offset;
> struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_FRAGMENT, AC_UD_PS_SAMPLE_POS_OFFSET);
> - uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_FRAGMENT, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
> + uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_FRAGMENT, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
> if (loc->sgpr_idx == -1)
> return;
> assert(loc->num_sgprs == 1);
> @@ -698,7 +698,7 @@ radv_emit_tess_shaders(struct radv_cmd_buffer *cmd_buffer,
>
> loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_CTRL, AC_UD_TCS_OFFCHIP_LAYOUT);
> if (loc->sgpr_idx != -1) {
> - uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_TESS_CTRL, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
> + uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_TESS_CTRL, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
> assert(loc->num_sgprs == 4);
> assert(!loc->indirect);
> radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 4);
> @@ -711,7 +711,7 @@ radv_emit_tess_shaders(struct radv_cmd_buffer *cmd_buffer,
>
> loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_EVAL, AC_UD_TES_OFFCHIP_LAYOUT);
> if (loc->sgpr_idx != -1) {
> - uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_TESS_EVAL, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
> + uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_TESS_EVAL, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
> assert(loc->num_sgprs == 1);
> assert(!loc->indirect);
>
> @@ -721,7 +721,7 @@ radv_emit_tess_shaders(struct radv_cmd_buffer *cmd_buffer,
>
> loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX, AC_UD_VS_LS_TCS_IN_LAYOUT);
> if (loc->sgpr_idx != -1) {
> - uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
> + uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
> assert(loc->num_sgprs == 1);
> assert(!loc->indirect);
>
> @@ -1319,7 +1319,7 @@ emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
> gl_shader_stage stage)
> {
> struct ac_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
> - uint32_t base_reg = shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
> + uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
>
> if (desc_set_loc->sgpr_idx == -1 || desc_set_loc->indirect)
> return;
> @@ -2621,7 +2621,7 @@ void radv_CmdDraw(
> struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
> AC_UD_VS_BASE_VERTEX_START_INSTANCE);
> if (loc->sgpr_idx != -1) {
> - uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(cmd_buffer->state.pipeline),
> + uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(cmd_buffer->state.pipeline),
> radv_pipeline_has_tess(cmd_buffer->state.pipeline));
> int vs_num = 2;
> if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id)
> @@ -2681,7 +2681,7 @@ void radv_CmdDrawIndexed(
> struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
> AC_UD_VS_BASE_VERTEX_START_INSTANCE);
> if (loc->sgpr_idx != -1) {
> - uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(cmd_buffer->state.pipeline),
> + uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(cmd_buffer->state.pipeline),
> radv_pipeline_has_tess(cmd_buffer->state.pipeline));
> int vs_num = 2;
> if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id)
> @@ -2741,7 +2741,7 @@ radv_emit_indirect_draw(struct radv_cmd_buffer *cmd_buffer,
>
> struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
> AC_UD_VS_BASE_VERTEX_START_INSTANCE);
> - uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(cmd_buffer->state.pipeline),
> + uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(cmd_buffer->state.pipeline),
> radv_pipeline_has_tess(cmd_buffer->state.pipeline));
> bool draw_id_enable = cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id;
> assert(loc->sgpr_idx != -1);
> diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
> index 5e629d7..e31ea2b 100644
> --- a/src/amd/vulkan/radv_private.h
> +++ b/src/amd/vulkan/radv_private.h
> @@ -1096,6 +1096,11 @@ static inline bool radv_pipeline_has_tess(struct radv_pipeline *pipeline)
> return pipeline->shaders[MESA_SHADER_TESS_EVAL] ? true : false;
> }
>
> +uint32_t radv_shader_stage_to_user_data_0(gl_shader_stage stage, bool has_gs, bool has_tess);
> +struct ac_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
> + gl_shader_stage stage,
> + int idx);
> +
> struct radv_graphics_pipeline_create_info {
> bool use_rectlist;
> bool db_depth_clear;
> --
> 2.9.4
>
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