[Mesa-dev] [PATCH 2/8] radeonsi: do EarlyCSEMemSSA LLVM pass

[Samuel Pitoiset]

On 06/07/2017 06:31 PM, Marek Olšák wrote:
> On Mon, Jun 5, 2017 at 10:32 PM, Samuel Pitoiset
> <samuel.pitoiset at gmail.com> wrote:
>>
>>
>> On 06/05/2017 06:50 PM, Marek Olšák wrote:
>>>
>>> From: Marek Olšák <marek.olsak at amd.com>
>>>
>>> so that LLVM IR looks like CSE has been run on it. It's also recommended
>>> by the instruction combining pass.
>>>
>>> This also fixes:
>>> - GL45-CTS.arrays_of_arrays_gl.InteractionFunctionCalls2 (crash)
>>> - piglit/spec/arb_shader_ballot/execution/fs-readFirstInvocation-uint-loop
>>> (fail)
>>>
>>> The code size decrease is positive, the register usage isn't. There is
>>> a decrease in VGPR spilling for Tomb Raider, but increase in DiRT Showdown
>>> and GRID Autosport.
>>>
>>> EarlyCSEMemSSA has a -0.01% change in code size compared EarlyCSE.
>>>
>>> SGPRS: 1935420 -> 1938076 (0.14 %)
>>> VGPRS: 1645504 -> 1645988 (0.03 %)
>>> Spilled SGPRs: 2493 -> 2651 (6.34 %)
>>> Spilled VGPRs: 107 -> 115 (7.48 %)
>>> Private memory VGPRs: 1332 -> 1332 (0.00 %)
>>> Scratch size: 1512 -> 1516 (0.26 %) dwords per thread
>>> Code Size: 61981592 -> 61890012 (-0.15 %) bytes
>>> Max Waves: 371847 -> 371798 (-0.01 %)
>>
>>
>> How about other games in your private shader-db? No changes?
> 
> No changes.
> 
>>
>> Any plans about how to decrease VGPR spilling for DiRT Showdown and GRID
>> Autosport? I'm asking because these games don't perform very well if I
>> remember correctly.
> 
> The spilling has no effect on DiRT Showdown performance. It just has
> one very slow pixel shader that doesn't spill.

Cool, thanks for confirming!

Samuel

> 
> Marek
> 
>>
>>
>>> ---
>>>    src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c | 2 ++
>>>    1 file changed, 2 insertions(+)
>>>
>>> diff --git a/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c
>>> b/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c
>>> index 1f8e913..802e2b9 100644
>>> --- a/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c
>>> +++ b/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c
>>> @@ -1444,20 +1444,22 @@ void si_llvm_optimize_module(struct
>>> si_shader_context *ctx)
>>>          LLVMAddAlwaysInlinerPass(gallivm->passmgr);
>>>          /* This pass should eliminate all the load and store instructions
>>> */
>>>          LLVMAddPromoteMemoryToRegisterPass(gallivm->passmgr);
>>>          /* Add some optimization passes */
>>>          LLVMAddScalarReplAggregatesPass(gallivm->passmgr);
>>>          LLVMAddLICMPass(gallivm->passmgr);
>>>          LLVMAddAggressiveDCEPass(gallivm->passmgr);
>>>          LLVMAddCFGSimplificationPass(gallivm->passmgr);
>>> +       /* This is recommended by the instruction combining pass. */
>>> +       LLVMAddEarlyCSEMemSSAPass(gallivm->passmgr);
>>>          LLVMAddInstructionCombiningPass(gallivm->passmgr);
>>>          /* Run the pass */
>>>          LLVMRunPassManager(gallivm->passmgr, ctx->gallivm.module);
>>>          LLVMDisposeBuilder(gallivm->builder);
>>>          LLVMDisposePassManager(gallivm->passmgr);
>>>          gallivm_dispose_target_library_info(target_library_info);
>>>    }
>>>