[Mesa-dev] [PATCH 2/2] RFC: radeon/compute: Limit allocations for VRAM-based chips to 3/4 VRAM

[Nicolai Hähnle]

On 08.06.2017 04:15, Michel Dänzer wrote:
> On 08/06/17 03:42 AM, Marek Olšák wrote:
>> On Wed, Jun 7, 2017 at 4:10 PM, Aaron Watry <awatry at gmail.com> wrote:
>>> On Mon, Jun 5, 2017 at 3:07 PM, Marek Olšák <maraeo at gmail.com> wrote:
>>>>
>>>> Can you make the change in radeon_drm_winsys.c instead?
>>>
>>> Something like the following?
>>>
>>> diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
>>> b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
>>> index a485615ae4..44948f49ef 100644
>>> --- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
>>> +++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
>>> @@ -365,6 +365,8 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
>>>       /* Radeon allocates all buffers as contigous, which makes large allocations
>>>        * unlikely to succeed. */
>>>       ws->info.max_alloc_size = MAX2(ws->info.vram_size,
>>> ws->info.gart_size) * 0.7;
>>> +    if (ws->info.has_dedicated_vram)
>>> +        ws->info.max_alloc_size = MIN2(ws->info.vram_size * 0.7,
>>> ws->info.max_alloc_size);
>>>       if (ws->info.drm_minor < 40)
>>>           ws->info.max_alloc_size = MIN2(ws->info.max_alloc_size, 256*1024*1024);
>>
>> Yes, feel free to push that.
> 
> That also affects PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE, is that intended?

Yes, that's actually good. We want to prevent applications from 
allocating buffers that are so large that we're likely to fail to put 
them in VRAM.

Cheers,
Nicolai
-- 
Lerne, wie die Welt wirklich ist,
Aber vergiss niemals, wie sie sein sollte.