[Mesa-dev] [PATCH 01/15] i965: Prepare blit engine for isl based miptrees

[Topi Pohjolainen]

Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
---
 src/mesa/drivers/dri/i965/intel_blit.c | 62 ++++++++++++++++++++++++++--------
 1 file changed, 48 insertions(+), 14 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_blit.c b/src/mesa/drivers/dri/i965/intel_blit.c
index e79e02a075..456c5e56bc 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.c
+++ b/src/mesa/drivers/dri/i965/intel_blit.c
@@ -131,6 +131,10 @@ set_blitter_tiling(struct brw_context *brw,
 static int
 blt_pitch(struct intel_mipmap_tree *mt)
 {
+   if (mt->surf.size > 0)
+      return (mt->surf.tiling != ISL_TILING_LINEAR) ?
+             mt->surf.row_pitch / 4 : mt->surf.row_pitch;
+
    int pitch = mt->pitch;
    if (mt->tiling)
       pitch /= 4;
@@ -171,8 +175,21 @@ get_blit_intratile_offset_el(const struct brw_context *brw,
                              uint32_t *x_offset_el,
                              uint32_t *y_offset_el)
 {
-   enum isl_tiling tiling = intel_miptree_get_isl_tiling(mt);
-   isl_tiling_get_intratile_offset_el(tiling, mt->cpp * 8, mt->pitch,
+   unsigned cpp;
+   unsigned pitch;
+   enum isl_tiling tiling;
+
+   if (mt->surf.size > 0) {
+      cpp = isl_format_get_layout(mt->surf.format)->bpb / 8;
+      pitch = mt->surf.row_pitch;
+      tiling = mt->surf.tiling;
+   } else {
+      cpp = mt->cpp;
+      pitch = mt->pitch;
+      tiling = intel_miptree_get_isl_tiling(mt);
+   }
+
+   isl_tiling_get_intratile_offset_el(tiling, cpp * 8, pitch,
                                       total_x_offset_el, total_y_offset_el,
                                       base_address_offset,
                                       x_offset_el, y_offset_el);
@@ -187,11 +204,11 @@ get_blit_intratile_offset_el(const struct brw_context *brw,
        * The offsets we get from ISL in the tiled case are already aligned.
        * In the linear case, we need to do some of our own aligning.
        */
-      assert(mt->pitch % 64 == 0);
+      assert(pitch % 64 == 0);
       uint32_t delta = *base_address_offset & 63;
-      assert(delta % mt->cpp == 0);
+      assert(delta % cpp == 0);
       *base_address_offset -= delta;
-      *x_offset_el += delta / mt->cpp;
+      *x_offset_el += delta / cpp;
    } else {
       assert(*base_address_offset % 4096 == 0);
    }
@@ -206,6 +223,17 @@ emit_miptree_blit(struct brw_context *brw,
                   uint32_t width, uint32_t height,
                   bool reverse, GLenum logicop)
 {
+   const unsigned src_cpp = src_mt->surf.size > 0 ?
+      isl_format_get_layout(src_mt->surf.format)->bpb / 8 : src_mt->cpp;
+   const unsigned src_pitch =
+      src_mt->surf.size > 0 ? src_mt->surf.row_pitch : src_mt->pitch;
+   const unsigned dst_pitch =
+      dst_mt->surf.size > 0 ? dst_mt->surf.row_pitch : dst_mt->pitch;
+   const unsigned src_tiling = src_mt->surf.size > 0 ?
+      isl_tiling_to_bufmgr_tiling(src_mt->surf.tiling) : src_mt->tiling;
+   const unsigned dst_tiling = dst_mt->surf.size > 0 ?
+      isl_tiling_to_bufmgr_tiling(dst_mt->surf.tiling) : dst_mt->tiling;
+
    /* According to the Ivy Bridge PRM, Vol1 Part4, section 1.2.1.2 (Graphics
     * Data Size Limitations):
     *
@@ -250,13 +278,13 @@ emit_miptree_blit(struct brw_context *brw,
                                       &dst_offset, &dst_tile_x, &dst_tile_y);
 
          if (!intelEmitCopyBlit(brw,
-                                src_mt->cpp,
-                                reverse ? -src_mt->pitch : src_mt->pitch,
+                                src_cpp,
+                                reverse ? -src_pitch : src_pitch,
                                 src_mt->bo, src_mt->offset + src_offset,
-                                src_mt->tiling,
-                                dst_mt->pitch,
+                                src_tiling,
+                                dst_pitch,
                                 dst_mt->bo, dst_mt->offset + dst_offset,
-                                dst_mt->tiling,
+                                dst_tiling,
                                 src_tile_x, src_tile_y,
                                 dst_tile_x, dst_tile_y,
                                 chunk_w, chunk_h,
@@ -327,11 +355,17 @@ intel_miptree_blit(struct brw_context *brw,
    intel_miptree_access_raw(brw, src_mt, src_level, src_slice, false);
    intel_miptree_access_raw(brw, dst_mt, dst_level, dst_slice, true);
 
-   if (src_flip)
-      src_y = minify(src_mt->physical_height0, src_level - src_mt->first_level) - src_y - height;
+   if (src_flip) {
+      const unsigned h0 = src_mt->surf.size > 0 ?
+         src_mt->surf.phys_level0_sa.height : src_mt->physical_height0;
+      src_y = minify(h0, src_level - src_mt->first_level) - src_y - height;
+   }
 
-   if (dst_flip)
-      dst_y = minify(dst_mt->physical_height0, dst_level - dst_mt->first_level) - dst_y - height;
+   if (dst_flip) {
+      const unsigned h0 = dst_mt->surf.size > 0 ?
+         dst_mt->surf.phys_level0_sa.height : dst_mt->physical_height0;
+      dst_y = minify(h0, dst_level - dst_mt->first_level) - dst_y - height;
+   }
 
    uint32_t src_image_x, src_image_y, dst_image_x, dst_image_y;
    intel_miptree_get_image_offset(src_mt, src_level, src_slice,
-- 
2.11.0