[Mesa-dev] [PATCH 11/15] i965/miptree: Add support for isl in readpixels_tiled_memcpy()

[Topi Pohjolainen]

Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
---
 src/mesa/drivers/dri/i965/intel_pixel_read.c | 27 ++++++++++++++++++---------
 1 file changed, 18 insertions(+), 9 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_pixel_read.c b/src/mesa/drivers/dri/i965/intel_pixel_read.c
index 871559edf9..3b68b437df 100644
--- a/src/mesa/drivers/dri/i965/intel_pixel_read.c
+++ b/src/mesa/drivers/dri/i965/intel_pixel_read.c
@@ -65,7 +65,7 @@
  */
 static bool
 intel_readpixels_tiled_memcpy(struct gl_context * ctx,
-                              GLint xoffset, GLint yoffset,
+                              unsigned xoffset, unsigned yoffset,
                               GLsizei width, GLsizei height,
                               GLenum format, GLenum type,
                               GLvoid * pixels,
@@ -126,9 +126,12 @@ intel_readpixels_tiled_memcpy(struct gl_context * ctx,
    if (!intel_get_memcpy(rb->Format, format, type, &mem_copy, &cpp))
       return false;
 
-   if (!irb->mt ||
-       (irb->mt->tiling != I915_TILING_X &&
-       irb->mt->tiling != I915_TILING_Y)) {
+   if (!irb->mt)
+      return false;
+
+   const uint32_t tiling = irb->mt->surf.size > 0 ?
+      isl_tiling_to_bufmgr_tiling(irb->mt->surf.tiling) : irb->mt->tiling;
+   if (tiling != I915_TILING_X && tiling != I915_TILING_Y) {
       /* The algorithm is written only for X- or Y-tiled memory. */
       return false;
    }
@@ -162,8 +165,11 @@ intel_readpixels_tiled_memcpy(struct gl_context * ctx,
       return false;
    }
 
-   xoffset += irb->mt->level[irb->mt_level].slice[irb->mt_layer].x_offset;
-   yoffset += irb->mt->level[irb->mt_level].slice[irb->mt_layer].y_offset;
+   unsigned image_offset_x, image_offset_y;
+   intel_miptree_get_image_offset(irb->mt, irb->mt_level, irb->mt_layer,
+                                  &image_offset_x, &image_offset_y);
+   xoffset += image_offset_x;
+   yoffset += image_offset_y;
 
    dst_pitch = _mesa_image_row_stride(pack, width, format, type);
 
@@ -189,18 +195,21 @@ intel_readpixels_tiled_memcpy(struct gl_context * ctx,
        "mesa_format=0x%x tiling=%d "
        "pack=(alignment=%d row_length=%d skip_pixels=%d skip_rows=%d)\n",
        __func__, xoffset, yoffset, width, height,
-       format, type, rb->Format, irb->mt->tiling,
+       format, type, rb->Format, tiling,
        pack->Alignment, pack->RowLength, pack->SkipPixels,
        pack->SkipRows);
 
+   const unsigned src_pitch =
+      irb->mt->surf.size > 0 ? irb->mt->surf.row_pitch : irb->mt->pitch;
+
    tiled_to_linear(
       xoffset * cpp, (xoffset + width) * cpp,
       yoffset, yoffset + height,
       pixels - (ptrdiff_t) yoffset * dst_pitch - (ptrdiff_t) xoffset * cpp,
       map + irb->mt->offset,
-      dst_pitch, irb->mt->pitch,
+      dst_pitch, src_pitch,
       brw->has_swizzling,
-      irb->mt->tiling,
+      tiling,
       mem_copy
    );
 
-- 
2.11.0