[Mesa-dev] [PATCH V2] intel/isl: Add the maximum surface size limit
Anuj Phogat
anuj.phogat at gmail.com
Thu Jun 15 21:40:35 UTC 2017
On Thu, Jun 15, 2017 at 1:51 PM, Nanley Chery <nanleychery at gmail.com> wrote:
> On Tue, May 23, 2017 at 04:12:38PM -0700, Anuj Phogat wrote:
>> V2: Use 2^31 bytes (2GB) surface size limit on pre-gen9 and
>> 2^38 bytes for gen9+.
>>
>> Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
>> ---
>> src/intel/isl/isl.c | 22 ++++++++++++++++++++++
>> 1 file changed, 22 insertions(+)
>>
>> diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
>> index 32aa698..812d106 100644
>> --- a/src/intel/isl/isl.c
>> +++ b/src/intel/isl/isl.c
>> @@ -1398,6 +1398,28 @@ isl_surf_init_s(const struct isl_device *dev,
>> base_alignment = MAX(info->min_alignment, tile_size);
>> }
>>
>> + if (ISL_DEV_GEN(dev) < 9) {
>> + /* From the Broadwell PRM Vol 5, Surface Layout:
>> + *
>> + * "In addition to restrictions on maximum height, width, and depth,
>> + * surfaces are also restricted to a maximum size in bytes. This
>> + * maximum is 2 GB for all products and all surface types.
>
> This block and the following are missing closing quotations. I think we
> can omit the opening quotes since you're doing a block quote. It's up to
> you though.
>
> With those two issues fixed, this series is
> Reviewed-by: Nanley Chery <nanley.g.chery at intel.com>
>
Fixed locally. Thanks.
>> + *
>> + * This comment is applicable to all Pre-gen9 platforms.
>> + */
>> + if (size > (uint64_t) 1 << 31)
>> + return false;
>> + } else {
>> + /* From the Skylake PRM Vol 5, Maximum Surface Size in Bytes:
>> + * "In addition to restrictions on maximum height, width, and depth,
>> + * surfaces are also restricted to a maximum size of 2^38 bytes.
>> + * All pixels within the surface must be contained within 2^38 bytes
>> + * of the base address.
>> + */
>> + if (size > (uint64_t) 1 << 38)
>> + return false;
>> + }
>> +
>> *surf = (struct isl_surf) {
>> .dim = info->dim,
>> .dim_layout = dim_layout,
>> --
>> 2.9.3
>>
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