[Mesa-dev] [PATCH 3/4] radeonsi/gfx9: fix TC-compatible stencil compression

[Marek Olšák]

From: Marek Olšák <marek.olsak at amd.com>

---
 src/amd/common/gfx9d.h                  | 4 ++--
 src/gallium/drivers/radeonsi/si_state.c | 6 ++++++
 2 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/src/amd/common/gfx9d.h b/src/amd/common/gfx9d.h
index 787d0a9..8c61645 100644
--- a/src/amd/common/gfx9d.h
+++ b/src/amd/common/gfx9d.h
@@ -1338,22 +1338,22 @@
 #define     V_008F14_IMG_DATA_FORMAT_ASTC_3D_LDR                    0x31 /* ditto */
 #define     V_008F14_IMG_DATA_FORMAT_ASTC_3D_HDR                    0x32 /* ditto */
 #define     V_008F14_IMG_DATA_FORMAT_ASTC_3D_LDR_SRGB               0x33 /* ditto */
 #define     V_008F14_IMG_DATA_FORMAT_N_IN_16                        0x34
 #define     V_008F14_IMG_DATA_FORMAT_N_IN_16_16                     0x35
 #define     V_008F14_IMG_DATA_FORMAT_N_IN_16_16_16_16               0x36
 #define     V_008F14_IMG_DATA_FORMAT_N_IN_16_AS_16_16_16_16         0x37
 #define     V_008F14_IMG_DATA_FORMAT_RESERVED_56                    0x38
 #define     V_008F14_IMG_DATA_FORMAT_4_4                            0x39
 #define     V_008F14_IMG_DATA_FORMAT_6_5_5                          0x3A
-#define     V_008F14_IMG_DATA_S8_16                                 0x3B
-#define     V_008F14_IMG_DATA_S8_32                                 0x3C
+#define     V_008F14_IMG_DATA_FORMAT_S8_16                          0x3B
+#define     V_008F14_IMG_DATA_FORMAT_S8_32                          0x3C
 #define     V_008F14_IMG_DATA_FORMAT_8_AS_32                        0x3D
 #define     V_008F14_IMG_DATA_FORMAT_8_AS_32_32                     0x3E
 #define     V_008F14_IMG_DATA_FORMAT_32_AS_32_32_32_32              0x3F
 #define   S_008F14_NUM_FORMAT_GFX9(x)                                 (((unsigned)(x) & 0x0F) << 26)
 #define   G_008F14_NUM_FORMAT_GFX9(x)                                 (((x) >> 26) & 0x0F)
 #define   C_008F14_NUM_FORMAT_GFX9                                    0xC3FFFFFF
 #define     V_008F14_IMG_NUM_FORMAT_UNORM                           0x00
 #define     V_008F14_IMG_NUM_FORMAT_SNORM                           0x01
 #define     V_008F14_IMG_NUM_FORMAT_USCALED                         0x02
 #define     V_008F14_IMG_NUM_FORMAT_SSCALED                         0x03
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 2a2c3c0..921f374 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -3239,20 +3239,26 @@ si_make_texture_descriptor(struct si_screen *screen,
 
 	/* Enable clamping for UNORM depth formats promoted to Z32F. */
 	if (screen->b.chip_class >= GFX9 &&
 	    util_format_has_depth(desc) &&
 	    num_format == V_008F14_IMG_NUM_FORMAT_FLOAT &&
 	    util_get_depth_format_type(base_desc) != UTIL_FORMAT_TYPE_FLOAT) {
 		/* NUM_FORMAT=FLOAT and DATA_FORMAT=24_8 means "clamp to [0,1]". */
 		data_format = V_008F14_IMG_DATA_FORMAT_24_8;
 	}
 
+	/* S8 with Z32 HTILE needs a special format. */
+	if (screen->b.chip_class >= GFX9 &&
+	    pipe_format == PIPE_FORMAT_S8_UINT &&
+	    tex->tc_compatible_htile)
+		data_format = V_008F14_IMG_DATA_FORMAT_S8_32;
+
 	if (!sampler &&
 	    (res->target == PIPE_TEXTURE_CUBE ||
 	     res->target == PIPE_TEXTURE_CUBE_ARRAY ||
 	     (screen->b.chip_class <= VI &&
 	      res->target == PIPE_TEXTURE_3D))) {
 		/* For the purpose of shader images, treat cube maps and 3D
 		 * textures as 2D arrays. For 3D textures, the address
 		 * calculations for mipmaps are different, so we rely on the
 		 * caller to effectively disable mipmaps.
 		 */
-- 
2.7.4