[Mesa-dev] [PATCH 8/9] radeonsi: don't emit partial flushes at the end of IBs

[Nicolai Hähnle]

On 19.06.2017 15:56, Marek Olšák wrote:
> On Mon, Jun 19, 2017 at 2:48 PM, Nicolai Hähnle <nhaehnle at gmail.com> wrote:
>> On 16.06.2017 14:58, Marek Olšák wrote:
>>>
>>> From: Marek Olšák <marek.olsak at amd.com>
>>>
>>> The kernel sort of does the same thing with fences.
>>
>>
>> The kernel sends an EVENT_WRITE_EOP with various TC flags. Is that
>> guaranteed to wait for shaders to finish and flush their data? I'm mostly
>> thinking about synchronizing with CPU reads here.
> 
> Yes, EOP events first wait and then they flush caches.

Okay.


>> While reading, I noticed that si_emit_cache_flush has a path where L1 is
>> invalidated _after_ L2 writeback. What's up with that? Couldn't it happen
>> that there's data in L1 which is not yet written to L2? Seems odd.
> 
> I have a vague memory that all stores go to L2 either immediately or
> at the end of waves, but I'm not sure.

I think you're right.

v2 of patch 7 & patch 8 are

Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>


> 
> Marek
> 


-- 
Lerne, wie die Welt wirklich ist,
Aber vergiss niemals, wie sie sein sollte.