[Mesa-dev] [PATCH 06/11] intel/genxml: Add Gen10 CACHE_MODE_1 definitions

[Anuj Phogat]

On Thu, Jun 22, 2017 at 9:18 AM, Rafael Antognolli
<rafael.antognolli at intel.com> wrote:
> On Tue, Jun 13, 2017 at 11:28:25AM -0700, Anuj Phogat wrote:
>> Few of the fields in this register are changed as compared
>> to gen9.xml.
>>
>> Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
>> ---
>>  src/intel/genxml/gen10.xml | 22 ++++++++++++++++++++++
>>  1 file changed, 22 insertions(+)
>>
>> diff --git a/src/intel/genxml/gen10.xml b/src/intel/genxml/gen10.xml
>> index d2bb130..e8776c7 100644
>> --- a/src/intel/genxml/gen10.xml
>> +++ b/src/intel/genxml/gen10.xml
>> @@ -3734,4 +3734,26 @@
>>      <field name="Sampler L2 Disable Mask" start="31" end="31" type="bool"/>
>>    </register>
>>
>> +  <register name="CACHE_MODE_1" length="1" num="0x7004">
>> +    <field name="Partial Resolve Disable In VC" start="1" end="1" type="bool"/>
>> +    <field name="RCZ PMA Promoted 2 Not-Promoted Allocation stall optimization Disable" start="3" end="3" type="bool"/>
>> +    <field name="MCS Cache Disable" start="5" end="5" type="bool"/>
>> +    <field name="4X4 RCPFE-STC Optimization Disable" start="6" end="6" type="bool"/>
>> +    <field name="Sampler Cache Set XOR selection" start="7" end="8" type="uint"/>
>> +    <field name="MSC RAW Hazard Avoidance Bit" start="9" end="9" type="bool"/>
>> +    <field name="NP Early Z Fails Disable" start="13" end="13" type="uint"/>
>> +    <field name="Blend Optimization Fix Disable" start="14" end="14" type="bool"/>
>> +    <field name="Color Compression Disable" start="15" end="15" type="bool"/>
>> +
>> +    <field name="Partial Resolve Disable In VC Mask" start="17" end="17" type="bool"/>
>> +    <field name="RCZ PMA Promoted 2 Not-Promoted Allocation stall optimization Disable Mask" start="19" end="19" type="bool"/>
>> +    <field name="MCS Cache Disable Mask" start="21" end="21" type="bool"/>
>> +    <field name="4X4 RCPFE-STC Optimization Disable Mask" start="22" end="22" type="bool"/>
>> +    <field name="Sampler Cache Set XOR selection Mask" start="23" end="24" type="uint"/>
>> +    <field name="MSC RAW Hazard Avoidance Bit Mask" start="25" end="25" type="bool"/>
>> +    <field name="NP Early Z Fails Disable Mask" start="29" end="29" type="bool"/>
>> +    <field name="Blend Optimization Fix Disable Mask" start="30" end="30" type="bool"/>
>> +    <field name="Color Compression Disable Mask" start="31" end="31" type="bool"/>
>> +  </register>
>
> Bit 14 and 1 changed name. Bits 8-6, and 4 seem to have been removed. And I
> believe the respective masks should be updated accordingly, right?
>
Bit 14 and 1 remains same on CNL. They are changed for future platforms.
I've removed bits 8-6 and 4. Thanks for the review.

> With that,
> Reviewed-by: Rafael Antognolli <rafael.antognolli at intel.com>
>
>>  </genxml>
>> --
>> 2.9.3
>>
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