[Mesa-dev] [PATCH 2/4] radv: set prim_id for geometry shaders

[Bas Nieuwenhuizen]

On Tue, Jun 20, 2017 at 6:38 AM, Dave Airlie <airlied at gmail.com> wrote:
> From: Dave Airlie <airlied at redhat.com>
>
> Noticed in passing.
>
> Signed-off-by: Dave Airlie <airlied at redhat.com>
> ---
>  src/amd/common/ac_nir_to_llvm.c | 5 +++--
>  src/amd/common/ac_nir_to_llvm.h | 1 +
>  src/amd/vulkan/si_cmd_buffer.c  | 6 ++++++
>  3 files changed, 10 insertions(+), 2 deletions(-)
>
> diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
> index 4d9c070..afef3fd 100644
> --- a/src/amd/common/ac_nir_to_llvm.c
> +++ b/src/amd/common/ac_nir_to_llvm.c
> @@ -3867,9 +3867,10 @@ static void visit_intrinsic(struct nir_to_llvm_context *ctx,
>                         result = ctx->gs_invocation_id;
>                 break;
>         case nir_intrinsic_load_primitive_id:
> -               if (ctx->stage == MESA_SHADER_GEOMETRY)
> +               if (ctx->stage == MESA_SHADER_GEOMETRY) {
> +                       ctx->shader_info->gs.uses_prim_id = true;
>                         result = ctx->gs_prim_id;
> -               else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
> +               } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
>                         ctx->shader_info->tcs.uses_prim_id = true;
>                         result = ctx->tcs_patch_id;
>                 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
> diff --git a/src/amd/common/ac_nir_to_llvm.h b/src/amd/common/ac_nir_to_llvm.h
> index 9ea3156..724d5e6 100644
> --- a/src/amd/common/ac_nir_to_llvm.h
> +++ b/src/amd/common/ac_nir_to_llvm.h
> @@ -178,6 +178,7 @@ struct ac_shader_variant_info {
>                         unsigned invocations;
>                         unsigned gsvs_vertex_size;
>                         unsigned max_gsvs_emit_size;
> +                       bool uses_prim_id;
>                 } gs;
>                 struct {
>                         bool uses_prim_id;
> diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
> index 962b76f..1525d44 100644
> --- a/src/amd/vulkan/si_cmd_buffer.c
> +++ b/src/amd/vulkan/si_cmd_buffer.c
> @@ -706,6 +706,7 @@ si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
>                     cmd_buffer->state.pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.uses_prim_id)
>                         ia_switch_on_eoi = true;
>
> +

Can you remove the extra blank line?

>                 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
>                 if ((family == CHIP_TAHITI ||
>                      family == CHIP_PITCAIRN ||
> @@ -789,6 +790,11 @@ si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
>                 partial_es_wave = true;
>
>         if (radv_pipeline_has_gs(cmd_buffer->state.pipeline)) {
> +
> +               if (radv_pipeline_has_gs(cmd_buffer->state.pipeline) &&
> +                   cmd_buffer->state.pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.uses_prim_id)
> +                       ia_switch_on_eoi = true;
> +
>                 /* GS requirement. */
>                 if (SI_GS_PER_ES / primgroup_size >= cmd_buffer->device->gs_table_depth - 3)
>                         partial_es_wave = true;
> --
> 2.9.4
>
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