[Mesa-dev] [PATCH 17/17] radeonsi: enable uniform packing

[Timothy Arceri]

---
 src/gallium/drivers/radeonsi/si_shader.c          |  4 ++--
 src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c | 10 ++++++++++
 src/mesa/state_tracker/st_context.c               |  2 ++
 3 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c
index 6c887dd..6808346 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -1744,38 +1744,38 @@ static LLVMValueRef fetch_constant(
 	if (swizzle == LP_CHAN_ALL) {
 		unsigned chan;
 		LLVMValueRef values[4];
 		for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
 			values[chan] = fetch_constant(bld_base, reg, type, chan);
 
 		return lp_build_gather_values(&ctx->gallivm, values, 4);
 	}
 
 	buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
-	idx = reg->Register.Index * 4 + swizzle;
+	idx = reg->Register.Index + swizzle;
 
 	if (reg->Register.Dimension && reg->Dimension.Indirect) {
 		LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
 		LLVMValueRef index;
 		index = si_get_bounded_indirect_index(ctx, &reg->DimIndirect,
 						      reg->Dimension.Index,
 						      ctx->num_const_buffers);
 		index = LLVMBuildAdd(ctx->gallivm.builder, index,
 				     LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS, 0), "");
 		bufp = ac_build_indexed_load_const(&ctx->ac, ptr, index);
 	} else
 		bufp = load_const_buffer_desc(ctx, buf);
 
 	if (reg->Register.Indirect) {
 		addr = ctx->addrs[ireg->Index][ireg->Swizzle];
 		addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
-		addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
+		addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 4);
 		addr = lp_build_add(&bld_base->uint_bld, addr,
 				    LLVMConstInt(ctx->i32, idx * 4, 0));
 	} else {
 		addr = LLVMConstInt(ctx->i32, idx * 4, 0);
 	}
 
 	result = buffer_load_const(ctx, bufp, addr);
 
 	if (!tgsi_type_is_64bit(type))
 		result = bitcast(bld_base, type, result);
diff --git a/src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c b/src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c
index 12f8de4..c65bf37 100644
--- a/src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c
+++ b/src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c
@@ -15,20 +15,21 @@
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  */
 
 #include "si_shader_internal.h"
+#include "gallivm/lp_bld_arit.h"
 #include "gallivm/lp_bld_const.h"
 #include "gallivm/lp_bld_intr.h"
 #include "gallivm/lp_bld_gather.h"
 #include "tgsi/tgsi_parse.h"
 #include "amd/common/ac_llvm_build.h"
 
 static void kill_if_fetch_args(struct lp_build_tgsi_context *bld_base,
 			       struct lp_build_emit_data *emit_data)
 {
 	const struct tgsi_full_instruction *inst = emit_data->inst;
@@ -249,20 +250,29 @@ static void emit_not(const struct lp_build_tgsi_action *action,
 }
 
 static void emit_arl(const struct lp_build_tgsi_action *action,
 		     struct lp_build_tgsi_context *bld_base,
 		     struct lp_build_emit_data *emit_data)
 {
 	LLVMBuilderRef builder = bld_base->base.gallivm->builder;
 	LLVMValueRef floor_index =  lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_FLR, emit_data->args[0]);
 	emit_data->output[emit_data->chan] = LLVMBuildFPToSI(builder,
 			floor_index, bld_base->base.int_elem_type , "");
+
+	/* radeonsi packs uniforms so we need to adjust the address to allow
+	 * for the component stride. We assume only asm programs will use
+	 * this opcode and multiply by stride of 4 as we don't pack asm
+	 * constants.
+	 */
+	emit_data->output[emit_data->chan] =
+		lp_build_mul_imm(&bld_base->uint_bld,
+				 emit_data->output[emit_data->chan], 4);
 }
 
 static void emit_and(const struct lp_build_tgsi_action *action,
 		     struct lp_build_tgsi_context *bld_base,
 		     struct lp_build_emit_data *emit_data)
 {
 	LLVMBuilderRef builder = bld_base->base.gallivm->builder;
 	emit_data->output[emit_data->chan] = LLVMBuildAnd(builder,
 			emit_data->args[0], emit_data->args[1], "");
 }
diff --git a/src/mesa/state_tracker/st_context.c b/src/mesa/state_tracker/st_context.c
index f57cd6a..cf04870 100644
--- a/src/mesa/state_tracker/st_context.c
+++ b/src/mesa/state_tracker/st_context.c
@@ -434,20 +434,22 @@ st_create_context_priv( struct gl_context *ctx, struct pipe_context *pipe,
    ctx->Point.MaxSize = MAX2(ctx->Const.MaxPointSize,
                              ctx->Const.MaxPointSizeAA);
    /* For vertex shaders, make sure not to emit saturate when SM 3.0 is not supported */
    ctx->Const.ShaderCompilerOptions[MESA_SHADER_VERTEX].EmitNoSat = !st->has_shader_model3;
 
    if (!ctx->Extensions.ARB_gpu_shader5) {
       for (i = 0; i < MESA_SHADER_STAGES; i++)
          ctx->Const.ShaderCompilerOptions[i].EmitNoIndirectSampler = true;
    }
 
+   ctx->Const.PackedDriverUniformStorage = true;
+
    /* Set which shader types can be compiled at link time. */
    st->shader_has_one_variant[MESA_SHADER_VERTEX] =
          st->has_shareable_shaders &&
          !st->clamp_vert_color_in_shader;
 
    st->shader_has_one_variant[MESA_SHADER_FRAGMENT] =
          st->has_shareable_shaders &&
          !st->clamp_frag_color_in_shader &&
          !st->force_persample_in_shader;
 
-- 
2.9.4