[Mesa-dev] [PATCH 45/92] ac/nir: use ac_shader_abi::emit_outputs

[Nicolai Hähnle]

From: Nicolai Hähnle <nicolai.haehnle at amd.com>

---
 src/amd/common/ac_nir_to_llvm.c | 16 ++++++++++++++--
 1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index bd913e5..6147af2 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -180,20 +180,27 @@ struct nir_to_llvm_context {
 
 	bool is_gs_copy_shader;
 	LLVMValueRef gs_next_vertex;
 	unsigned gs_max_out_vertices;
 
 	unsigned tes_primitive_mode;
 	uint64_t tess_outputs_written;
 	uint64_t tess_patch_outputs_written;
 };
 
+static inline struct nir_to_llvm_context *
+nir_to_llvm_context_from_abi(struct ac_shader_abi *abi)
+{
+	struct nir_to_llvm_context *ctx = NULL;
+	return container_of(abi, ctx, abi);
+}
+
 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
 				     const nir_deref_var *deref,
 				     enum desc_type desc_type);
 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
 {
 	return (index * 4) + chan;
 }
 
 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
 {
@@ -5704,22 +5711,25 @@ handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
 	ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
 }
 
 static void
 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
 {
 	ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
 }
 
 static void
-handle_shader_outputs_post(struct nir_to_llvm_context *ctx)
+handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
+			   LLVMValueRef *addrs)
 {
+	struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
+
 	switch (ctx->stage) {
 	case MESA_SHADER_VERTEX:
 		if (ctx->options->key.vs.as_ls)
 			handle_ls_outputs_post(ctx);
 		else if (ctx->options->key.vs.as_es)
 			handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
 		else
 			handle_vs_outputs_post(ctx, &ctx->shader_info->vs.outinfo);
 		break;
 	case MESA_SHADER_FRAGMENT:
@@ -5887,21 +5897,22 @@ void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
 	ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
 	                                   _mesa_key_pointer_equal);
 
 	func = (struct nir_function *)exec_list_get_head(&nir->functions);
 
 	setup_locals(&ctx, func);
 
 	visit_cf_list(&ctx, &func->impl->body);
 	phi_post_pass(&ctx);
 
-	handle_shader_outputs_post(nctx);
+	ctx.abi->emit_outputs(ctx.abi, RADEON_LLVM_MAX_OUTPUTS,
+			      ctx.outputs);
 
 	free(ctx.locals);
 	ralloc_free(ctx.defs);
 	ralloc_free(ctx.phis);
 
 	if (nctx)
 		nctx->nir = NULL;
 }
 
 static
@@ -5983,20 +5994,21 @@ LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
 	ctx.num_output_clips = nir->info.clip_distance_array_size;
 	ctx.num_output_culls = nir->info.cull_distance_array_size;
 
 	nir_foreach_variable(variable, &nir->inputs)
 		handle_shader_input_decl(&ctx, variable);
 
 	if (nir->stage == MESA_SHADER_FRAGMENT)
 		handle_fs_inputs_pre(&ctx, nir);
 
 	ctx.abi.inputs = &ctx.inputs[0];
+	ctx.abi.emit_outputs = handle_shader_outputs_post;
 
 	ac_nir_translate(&ctx.ac, &ctx.abi, nir, &ctx);
 
 	LLVMBuildRetVoid(ctx.builder);
 
 	ac_llvm_finalize_module(&ctx);
 
 	ac_nir_eliminate_const_vs_outputs(&ctx);
 
 	if (nir->stage == MESA_SHADER_GEOMETRY) {
-- 
2.9.3