[Mesa-dev] [PATCH] nvc0: increase alignment to 256 for texture buffers on fermi

[Ilia Mirkin]

On Wed, Mar 1, 2017 at 11:54 AM, Roland Scheidegger <sroland at vmware.com> wrote:
> Am 01.03.2017 um 17:09 schrieb Ilia Mirkin:
>> When binding as textures, the alignment can be 16. However when binding
>> as an image, the address has to be aligned to 256. (Also when binding as
>> an RT, but that can't happen with GL or current gallium APIs.)
> FWIW binding buffers as rt is fully supported with gallium (it's a dx10
> feature). But I guess outside of llvmpipe and our internal state tracker
> it's unused...

Noted. I'll remove the bit about gallium before pushing.

>
>>
>> Reported-by: Roy Spliet <nouveau at spliet.org>
>> Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
>> ---
>>  src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 4 +++-
>>  1 file changed, 3 insertions(+), 1 deletion(-)
>>
>> diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
>> index 25c60f9..643eb43 100644
>> --- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
>> +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
>> @@ -147,7 +147,9 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
>>     case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
>>        return 256;
>>     case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
>> -      return 16; /* 256 for binding as RT, but that's not possible in GL */
>> +      if (class_3d < NVE4_3D_CLASS)
>> +         return 256; /* IMAGE bindings require alignment to 256 */
>> +      return 16;
>>     case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
>>        return 16;
>>     case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
>>
>