[Mesa-dev] [PATCH 01/24] i965: Move a couple of #defines from brw_context to brw_compiler

[Anuj Phogat]

On Tue, Feb 28, 2017 at 9:03 PM, Jason Ekstrand <jason at jlekstrand.net> wrote:
> ---
>  src/mesa/drivers/dri/i965/brw_compiler.h | 16 ++++++++++++++++
>  src/mesa/drivers/dri/i965/brw_context.h  | 18 ------------------
>  2 files changed, 16 insertions(+), 18 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_compiler.h b/src/mesa/drivers/dri/i965/brw_compiler.h
> index 3b3b7e0..297d8f8 100644
> --- a/src/mesa/drivers/dri/i965/brw_compiler.h
> +++ b/src/mesa/drivers/dri/i965/brw_compiler.h
> @@ -492,6 +492,22 @@ typedef enum
>  } brw_varying_slot;
>
>  /**
> + * We always program SF to start reading at an offset of 1 (2 varying slots)
> + * from the start of the vertex URB entry.  This causes it to skip:
> + * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
> + * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
> + */
> +#define BRW_SF_URB_ENTRY_READ_OFFSET 1
> +
> +/**
> + * Bitmask indicating which fragment shader inputs represent varyings (and
> + * hence have to be delivered to the fragment shader by the SF/SBE stage).
> + */
> +#define BRW_FS_VARYING_INPUT_MASK \
> +   (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
> +    ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
> +
> +/**
>   * Data structure recording the relationship between the gl_varying_slot enum
>   * and "slots" within the vertex URB entry (VUE).  A "slot" is defined as a
>   * single octaword within the VUE (128 bits).
> diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
> index 7ff7b74..c9a931c 100644
> --- a/src/mesa/drivers/dri/i965/brw_context.h
> +++ b/src/mesa/drivers/dri/i965/brw_context.h
> @@ -328,15 +328,6 @@ struct brw_program {
>  };
>
>
> -/**
> - * Bitmask indicating which fragment shader inputs represent varyings (and
> - * hence have to be delivered to the fragment shader by the SF/SBE stage).
> - */
> -#define BRW_FS_VARYING_INPUT_MASK \
> -   (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
> -    ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
> -
> -
>  struct brw_sf_prog_data {
>     GLuint urb_read_length;
>     GLuint total_grf;
> @@ -351,15 +342,6 @@ struct brw_sf_prog_data {
>  };
>
>
> -/**
> - * We always program SF to start reading at an offset of 1 (2 varying slots)
> - * from the start of the vertex URB entry.  This causes it to skip:
> - * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
> - * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
> - */
> -#define BRW_SF_URB_ENTRY_READ_OFFSET 1
> -
> -
>  struct brw_clip_prog_data {
>     GLuint curb_read_length;    /* user planes? */
>     GLuint clip_mode;
> --
> 2.5.0.400.gff86faf
>
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Patches 1-7 are:
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>

I noticed that Matt and Ken have already finished reviewing this series.
So, I won't review rest of the series.