[Mesa-dev] [PATCH] i965: Rename brw_format_for_mesa_format() to brw_isl_format_for_mesa_format()
Pohjolainen, Topi
topi.pohjolainen at gmail.com
Thu Mar 9 07:14:40 UTC 2017
On Sat, Mar 04, 2017 at 07:44:17AM -0800, Jason Ekstrand wrote:
> Hopefully, this doesn't conflict too badly with what Topi is doing. If not,
Oh, sorry, almost forgot to reply, This is fine by me. It is easy rebase if
not even that.
>
> Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
>
>
> On March 3, 2017 2:40:41 PM Anuj Phogat <anuj.phogat at gmail.com> wrote:
>
> > Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
> > ---
> > src/mesa/drivers/dri/i965/brw_blorp.c | 2 +-
> > src/mesa/drivers/dri/i965/brw_context.c | 2 +-
> > src/mesa/drivers/dri/i965/brw_meta_util.c | 2 +-
> > src/mesa/drivers/dri/i965/brw_state.h | 2 +-
> > src/mesa/drivers/dri/i965/brw_surface_formats.c | 14 +++++++-------
> > src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 4 ++--
> > src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 2 +-
> > 7 files changed, 14 insertions(+), 14 deletions(-)
> >
> > diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c
> > b/src/mesa/drivers/dri/i965/brw_blorp.c
> > index 9f7ba3d..fdc9dd1 100644
> > --- a/src/mesa/drivers/dri/i965/brw_blorp.c
> > +++ b/src/mesa/drivers/dri/i965/brw_blorp.c
> > @@ -294,7 +294,7 @@ brw_blorp_to_isl_format(struct brw_context *brw,
> > mesa_format format,
> > assert(brw->format_supported_as_render_target[format]);
> > return brw->render_target_format[format];
> > } else {
> > - return brw_format_for_mesa_format(format);
> > + return brw_isl_format_for_mesa_format(format);
> > }
> > break;
> > }
> > diff --git a/src/mesa/drivers/dri/i965/brw_context.c
> > b/src/mesa/drivers/dri/i965/brw_context.c
> > index 3688ba4..42dfed0 100644
> > --- a/src/mesa/drivers/dri/i965/brw_context.c
> > +++ b/src/mesa/drivers/dri/i965/brw_context.c
> > @@ -205,7 +205,7 @@ intel_texture_view_requires_resolve(struct
> > brw_context *brw,
> > !intel_miptree_is_lossless_compressed(brw, intel_tex->mt))
> > return false;
> >
> > - const uint32_t brw_format = brw_format_for_mesa_format(intel_tex->_Format);
> > + const uint32_t brw_format =
> > brw_isl_format_for_mesa_format(intel_tex->_Format);
> >
> > if (isl_format_supports_ccs_e(&brw->screen->devinfo, brw_format))
> > return false;
> > diff --git a/src/mesa/drivers/dri/i965/brw_meta_util.c
> > b/src/mesa/drivers/dri/i965/brw_meta_util.c
> > index 07a160f..cbc2ded 100644
> > --- a/src/mesa/drivers/dri/i965/brw_meta_util.c
> > +++ b/src/mesa/drivers/dri/i965/brw_meta_util.c
> > @@ -288,7 +288,7 @@ brw_is_color_fast_clear_compatible(struct brw_context *brw,
> > * this case. At least on Gen9 this really does seem to cause problems.
> > */
> > if (brw->gen >= 9 &&
> > - brw_format_for_mesa_format(mt->format) !=
> > + brw_isl_format_for_mesa_format(mt->format) !=
> > brw->render_target_format[mt->format])
> > return false;
> >
> > diff --git a/src/mesa/drivers/dri/i965/brw_state.h
> > b/src/mesa/drivers/dri/i965/brw_state.h
> > index 4b7e3c2..bd05b60 100644
> > --- a/src/mesa/drivers/dri/i965/brw_state.h
> > +++ b/src/mesa/drivers/dri/i965/brw_state.h
> > @@ -267,7 +267,7 @@ void gen4_init_vtable_surface_functions(struct
> > brw_context *brw);
> > uint32_t brw_get_surface_tiling_bits(uint32_t tiling);
> > uint32_t brw_get_surface_num_multisamples(unsigned num_samples);
> >
> > -uint32_t brw_format_for_mesa_format(mesa_format mesa_format);
> > +uint32_t brw_isl_format_for_mesa_format(mesa_format mesa_format);
> >
> > GLuint translate_tex_target(GLenum target);
> >
> > diff --git a/src/mesa/drivers/dri/i965/brw_surface_formats.c
> > b/src/mesa/drivers/dri/i965/brw_surface_formats.c
> > index 706818d..7b17e11 100644
> > --- a/src/mesa/drivers/dri/i965/brw_surface_formats.c
> > +++ b/src/mesa/drivers/dri/i965/brw_surface_formats.c
> > @@ -29,7 +29,7 @@
> > #include "brw_defines.h"
> >
> > uint32_t
> > -brw_format_for_mesa_format(mesa_format mesa_format)
> > +brw_isl_format_for_mesa_format(mesa_format mesa_format)
> > {
> > /* This table is ordered according to the enum ordering in formats.h. We do
> > * expect that enum to be extended without our explicit initialization
> > @@ -303,7 +303,7 @@ brw_init_surface_formats(struct brw_context *brw)
> > uint32_t texture, render;
> > bool is_integer = _mesa_is_format_integer_color(format);
> >
> > - render = texture = brw_format_for_mesa_format(format);
> > + render = texture = brw_isl_format_for_mesa_format(format);
> >
> > /* The value of ISL_FORMAT_R32G32B32A32_FLOAT is 0, so don't skip
> > * it.
> > @@ -536,7 +536,7 @@ translate_tex_format(struct brw_context *brw,
> > return ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS;
> >
> > case MESA_FORMAT_RGBA_FLOAT32:
> > - /* The value of this BRW_SURFACEFORMAT is 0, which tricks the
> > + /* The value of this ISL surface format is 0, which tricks the
> > * assertion below.
> > */
> > return ISL_FORMAT_R32G32B32A32_FLOAT;
> > @@ -550,7 +550,7 @@ translate_tex_format(struct brw_context *brw,
> > WARN_ONCE(true, "Demoting sRGB DXT1 texture to non-sRGB\n");
> > mesa_format = MESA_FORMAT_RGB_DXT1;
> > }
> > - return brw_format_for_mesa_format(mesa_format);
> > + return brw_isl_format_for_mesa_format(mesa_format);
> >
> > case MESA_FORMAT_RGBA_ASTC_4x4:
> > case MESA_FORMAT_RGBA_ASTC_5x4:
> > @@ -566,7 +566,7 @@ translate_tex_format(struct brw_context *brw,
> > case MESA_FORMAT_RGBA_ASTC_10x10:
> > case MESA_FORMAT_RGBA_ASTC_12x10:
> > case MESA_FORMAT_RGBA_ASTC_12x12: {
> > - GLuint brw_fmt = brw_format_for_mesa_format(mesa_format);
> > + GLuint brw_fmt = brw_isl_format_for_mesa_format(mesa_format);
> >
> > /**
> > * It is possible to process these formats using the LDR Profile
> > @@ -583,8 +583,8 @@ translate_tex_format(struct brw_context *brw,
> > }
> >
> > default:
> > - assert(brw_format_for_mesa_format(mesa_format) != 0);
> > - return brw_format_for_mesa_format(mesa_format);
> > + assert(brw_isl_format_for_mesa_format(mesa_format) != 0);
> > + return brw_isl_format_for_mesa_format(mesa_format);
> > }
> > }
> >
> > diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> > b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> > index 8ffbc0a..827057a 100644
> > --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> > +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> > @@ -687,7 +687,7 @@ brw_update_buffer_texture_surface(struct gl_context *ctx,
> > uint32_t size = tObj->BufferSize;
> > drm_intel_bo *bo = NULL;
> > mesa_format format = tObj->_BufferObjectFormat;
> > - uint32_t brw_format = brw_format_for_mesa_format(format);
> > + uint32_t brw_format = brw_isl_format_for_mesa_format(format);
> > int texel_size = _mesa_get_format_bytes(format);
> >
> > if (intel_obj) {
> > @@ -1580,7 +1580,7 @@ static uint32_t
> > get_image_format(struct brw_context *brw, mesa_format format, GLenum access)
> > {
> > const struct gen_device_info *devinfo = &brw->screen->devinfo;
> > - uint32_t hw_format = brw_format_for_mesa_format(format);
> > + uint32_t hw_format = brw_isl_format_for_mesa_format(format);
> > if (access == GL_WRITE_ONLY) {
> > return hw_format;
> > } else if (isl_has_matching_typed_storage_image_format(devinfo, hw_format)) {
> > diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> > b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> > index b339f99..3295175 100644
> > --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> > +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> > @@ -209,7 +209,7 @@ intel_miptree_supports_non_msrt_fast_clear(struct
> > brw_context *brw,
> >
> > if (brw->gen >= 9) {
> > mesa_format linear_format = _mesa_get_srgb_format_linear(mt->format);
> > - const uint32_t brw_format = brw_format_for_mesa_format(linear_format);
> > + const uint32_t brw_format =
> > brw_isl_format_for_mesa_format(linear_format);
> > return isl_format_supports_ccs_e(&brw->screen->devinfo, brw_format);
> > } else
> > return true;
> > --
> > 2.9.3
> >
> > _______________________________________________
> > mesa-dev mailing list
> > mesa-dev at lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/mesa-dev
>
>
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